參數(shù)資料
型號: VS3V125QX
廠商: Vaishali Semiconductor
英文描述: 3.3V Quad Bus Switch with Individual Active Low Enables
中文描述: 3.3四總線開關(guān)與個別現(xiàn)行低啟用
文件頁數(shù): 1/6頁
文件大?。?/td> 62K
代理商: VS3V125QX
2001-04-12
Page 1
MDSS-0002-02
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Applications
=
3.3v to 2.5V translation
=
2.5V to 1.8V translation
=
Hot Swapping
=
Bus switching
=
=
Clock gating
Logic replacement
General Description
The VS3V125 contains a set of four high-speed, low-resistance bus switches. Each bus switch is individually
controlled by LVTTL-compatible, active-low control input (/xOE). The low ON resistance of VS3V125 allows
inputs to be connected to outputs without adding propagation delay and without generating additional signal
noise.
The VS3V125 is designed for 3.3V to 2.5V, or 2.5V to 1.8V level translation, without any external
components. In addition, the high off-isolation between switch terminals in the ‘disable’ mode, and the near-
zero propagation delay in the ‘on’ state make the VS3V125 an ideal interface element for hot-swapping
applications.
Features
=
Enhanced N-FET with no dc path to V
CC
or
GND in normal operating signal voltage range.
=
Low impedance bidirectional data flow
=
Pin-compatible with CBTLV3215 switch
=
Zero added ground bounce or signal noise
=
LVTTL-compatible control signals
=
Undershoot clamp diodes on all
switch and control pins
ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
Latch-up current >100mA
Available in 150-mil wide QSOP
package
=
=
=
Figure 1. Functional Block Diagram
Figure 2. Pin Configuration
VS3V125
3.3V Quad Bus Switch with
Individual Active Low Enables
QSOP
NC
/1OE
1A
1Y
/2OE
2A
2Y
/4OE
4A
4Y
/3OE
3A
3Y
GND
V
CC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
All Pins, Top View
NC= No Connect
1A
2A
3A
4A
1Y
2Y
3Y
4Y
/1OE
/2OE
/3OE
/4OE
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