參數(shù)資料
型號: VS3V257Q
廠商: Vaishali Semiconductor
英文描述: High-speed 3.3V CMOS VSwitch Quad 2:1 Mux/Demux
中文描述: 高速3.3V CMOS電vSwitch上四2:1復(fù)用/解復(fù)用
文件頁數(shù): 1/6頁
文件大?。?/td> 60K
代理商: VS3V257Q
2000-11-28
Page 1
MDSS-0001-01
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Applications
=
3.3V to 2.5V translation
=
2.5V to 1.8V translation
=
Hot-Swapping
=
=
Logic replacement
Memory bank, video, and audio
switching
General Description
The VS3V257 is a high-speed LVTTL–compatible Quad 2:1 multiplexer/demultiplexer. The VS3V257
contains four mux/demux channels, with a common path control (S) and active low enable (/E). The low ON
resistance of the VS3V257 allows inputs to be connected to outputs, without adding propagation delay and
without generating additional signal noise. The VS3V2257 has 25
resistors in series with the switches to
reduce ground-bounce noise and signal reflection.
The VS3V257 and VS3V2257 are designed for 3.3V to 2.5V or 2.5V to 1.8V level translation, without any
external components. These switches also offer very high impedance between switch terminals in the
power-off or “disabled” state. This feature, combined with near-zero propagation delay in the “on” state,
makes VS3V257 and VS3V2257 ideal interface elements for hot-swapping applications.
VS3V257 / VS3V2257
High-speed 3.3V CMOS VSwitch
Quad 2:1 Mux/Demux
Features
=
Enhanced N-FET with no DC path to V
CC
or GND in normal operating signal voltage
range.
=
Low impedance switches connect inputs to
outputs with near-zero propagation delay:
5
(VS3V257) and 25
(VS3V2257)
=
Pin-compatible with 74LVC257 or
equivalent logic devices
=
Zero added ground bounce or signal noise
=
=
Break-before-make feature
Undershoot clamp diodes on all switch and
control pins
ESD rating >2000V (Human Body Model)
or >200V (Machine Model)
Latch-up current >100mA
Available in 150-mil wide QSOP package
=
=
=
=
(All Pins Top View)
I0
A
I1
A
I0
B
I1
B
I0
C
I1
C
I0
D
I1
D
S
/E
Y
A
Y
B
Y
C
Y
D
I1
D
Y
D
I0
C
I1
C
Y
C
I0
D
QSOP
/E
V
CC
GND
S
I0
A
I1
A
Y
A
I0
B
I1
B
Y
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 1. Functional Block Diagram
Figure 2. Pin Configuration
相關(guān)PDF資料
PDF描述
VS3V257QX High-speed 3.3V CMOS VSwitch Quad 2:1 Mux/Demux
VS3V2257QX High-speed 3.3V CMOS VSwitch Quad 2:1 Mux/Demux
VS3V253QX High-speed 3.3V CMOS VSwitch Dual 4:1 Mux/Demux
VS3V2253QX High-speed 3.3V CMOS VSwitch Dual 4:1 Mux/Demux
VS3V2253Q High-speed 3.3V CMOS VSwitch Dual 4:1 Mux/Demux
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