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參數(shù)資料
| 型號： | VRC4171A |
| 廠商： | NEC Corp. |
| 英文描述： | Companion Chip for VR4100 Family MIPS RISC Microprocessor(VR4100系列RSIC微處理器的配對芯片) |
| 中文描述： | 同伴芯片為VR4100家庭的MIPS RISC微處理器（VR4100系列重結(jié)晶微處理器的配對芯片） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 114K |
| 代理商： | VRC4171A |
7
V
RC
4171A Companion Chip
Note:
All values are subject to change without notice.
Table 6. Uncharacterized AC Characteristics
(refer to Figure 3)
Parameter
Symbol
Min.
Typ.
Max.
Unit
BUSCLK clock period
t
100
125
ns
Slot A Only
ns
*MEMCS16, *IOCS16
↓
delay from SA[23:0] address and *SBHE valid
t
101
8
15
ns
*MEMCS16, *IOCS16
↓
hold time from BUSCLK
↑
t
102
3
4
ns
*A_CE[2:1], *A_REG
↓
delay from SA[23:0] address and *SBHE valid
t
103
9
15
ns
A_ADR[25:0] address valid delay from SA[23:0] address and *SBHE valid
t
104
5
9
ns
IOCHRDY valid delay from *SMRD, *SMWR, *SIORD, *SIOWR
↓
t
105
4
7
ns
IOCHRDY hold time from BUSCLK
↓
t
106
4
7
ns
*A_OE, *A_WE
↓
delay from *SMRD, *SMWR
↓
t
107
6
10
ns
*A_IOR, *A_IOW
↓
delay from *SIORD, *SIOWR
↓
t
108
7
12
ns
*A_CE[2:1], *A_REG
↑
delay from *SMRD, *SMWR, *SIORD, *SIOWR
↑
t
109
9
15
ns
*A_OE, *A_WE
↑
delay from *SMRD, *SMWR
↑
t
110
6
10
ns
*A_IOR, *A_IOW
↑
delay from *SIORD, *SIOWR
↑
t
111
7
12
ns
SD[15:0] data valid to A_D[15:0] valid delay (write cycle)
t
112
13
17
ns
SD[15:0] data valid delay from A_D[15:0] valid (read cycle)
t
113
6
9
ns
SD[
15:0
] data hold time from *SMRD, *SMWR,*SIORD,*SIOWR
↑
(
read cycle
)
t
114
4
6
9
ns
Slot A in Dual Slot Mode
ns
A_DBUFDIR delay from *SMRD, *SMWR, *SIORD, *SIOWR
↓
t
115
6
9
ns
A_DBUFDIR hold time to *SMRD, *SMWR, *SIORD, *SIOWR
↑
t
116
4
7
ns
A_DBUFEN[2:1] delay from *SMRD, *SMWR, *SIORD, *SIOWR
↓
t
117
9
13
ns
A_DBUFEN[2:1] hold time to *SMRD, *SMWR, *SIORD, *SIOWR
↑
t
118
5
8
ns
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