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參數(shù)資料
| 型號(hào)： | VRC5074 |
| 廠商： | NEC Corp. |
| 英文描述： | Interface Controller(接口控制器) |
| 中文描述： | 接口控制器（接口控制器） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 27K |
| 代理商： | VRC5074 |
U12926EU1V0PB00
Product Brief (Preliminary)
August 1997
NEC Electronics Inc.
V
RC
5074
Interface Controller for the
V
R
5000 Microprocessor
Description
The V
RC
V
R
5000
The V
RC
PCI bus with no buffering required. The DRAM memory interface connecting to local
memory contains the logic required to directly drive several types and speeds of SDRAM.
The interface control logic is highly configurable by software and can be used with mini-
mal hardware configuration in many different types of systems. The local bus interface
connecting to local I/O contains the interface logic necessary to directly drive several
types and speeds of peripheral devices.
5074
TM
processor and a DRAM memory system, local I/O bus, and standard PCI bus.
5074 interface controller connects directly to the V
TM
is a single-chip device that provides a glueless interface between a
R
5000 microprocessor and
V
Glueless interface to V
3.3-volt I/O
Support for all
ed for non-block writes)
Fifteen interrupt sources, individually enabled and individually assigned to one of the
V
R
5000's seven interrupt pins
Bi-endian
Multiple V
RC
5074 supported with a single V
R
5000 Interface
R
5000 microprocessor
V
R
5000
bus cycle types and combinations (pipelined write only support-
R
5000
Internal Registers
Physical device address registers with flexible physical address decoding for local I/O
devices, memory, and PCI
V
R
5000 interface control registers
Main memory control registers
PCI control registers
Local bus interface control registers
DMA controller registers
UART registers
Timer registers
PCI configuration registers
Main Memory Interface
Three banks of memory: two SDRAM and one non-SDRAM
— Programmable address ranges for each bank
— Interleaved or noninterleaved (interleaving buffers internal to the V
Four types of SDRAM: four-bank 256M and 64M; two-bank 64M and 16M
Multiple open SDRAM pages
ECC and parity supported
Built-in refresh operation
3.3-volt outputs; 5-volt-tolerant inputs
RC
5074)
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