參數(shù)資料
型號: VPX322XE
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁數(shù): 7/92頁
文件大?。?/td> 567K
代理商: VPX322XE
ADVANCE INFORMATION
VPX 322xE
7
Micronas
1.1. System Architecture
The block diagram (Fig. 1
1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YC
b
C
r
samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note:
The VPX 322xE is register compatible with the
VPX 322xD family, but not with VPX 3220A, VPX 3216B,
and VPX 3214C family.
T
T
T
T
R
Clock Gen.
DCO
ADC
Sync Processing
Text Slicer
(not VPX 3224E)
Chroma
Demodulator
Line Store
Luma Filter
Video Decoder
M
ADC
I2C
JTAG
V
V
CVBS/Y
Chroma
SDA
SCL
HREF
VREF
FIELD
A[7:0]
OEQ
B[7:0]
PIXCLK
LLC
VACT
Y
Y
C
b
C
r
C
b
C
r
M
M
P
P
A
(
Fig. 1–1:
Block diagram of the VPX 322xE
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