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參數(shù)資料
| 型號(hào)： | VP510CGGPFR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Bi Directional Colour Space Converter |
| 中文描述： | 8-BIT, DSP-VIDEO IMAGING, PQCC100 |
| 封裝： | PLASTIC, LCC-100 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 312K |
| 代理商： | VP510CGGPFR |
VP 510
7
Internally the luminance component obtained from the
decimating filter is represented by the 10 least significant
integer bits plus 3 fractional bits. The 10 integer bits accom-
modate any undershoot or overshoot caused by the filter. If the
most significant fractional bit is set, then the integer bits are
incremented by one. The resulting 10 bit signed integer value
,representing
±
512, is then clipped to provide an 8 bit, positive
only, number. Negative values become zero, and values
greater than 255 will saturate at 255.
The NORM bit in the Control Register determines which
bits out of the 15.3 available are selected from the outputs of
the chrominance filters. The choice is illustrated in Figure 4. If
the user is working with normalized chrominance, then the
matrix coefficients will have been chosen to produce outputs
in the range of
±
128 ( representing
±
0.5 ). This range only
requires 8 signed integer bits, and the ninth bit going into the
filter will be a repeated sign bit. The 9 least significant integer
bits are then selected out of the 15 available from the output
of the filter. These are then sufficient to accommodate any
undershoot and overshoot beyond the 8 bit input, and are
rounded with the most significant fractional bit. The resulting
9 bit signed value is clipped to an 8 bit signed number with a
range of
±
128, representing
±
0.5. Values outside the range
are clipped to the maximum values allowed.
When chrominance is not normalized the range becomes
±
1, or
±
256 in our internal notation. This range needs all 9 bits
of the integer component going into the filter, and requires 10
integer bits coming out of the filter to allow for undershoot and
overshoot. The 9 bit value expected by the clipping circuit is
now produced by using the least significant integer bit to round
the next 9 integer bits. This word is then clipped to an 8 bit
signed value with a range of
±
128, but now representing
±
1
since higher order bits were selected at the output of the filter.
If the BYPASS bit is set in the Control Register, these
values are passed directly to the output pins. If this bit is reset
they are further modified in a manner determined by the SEL
bit in the Control Register. This is illustrated in Figure 8.
If the SEL bit is set, then zero luminance values become
1 and value 255 is clipped at 254. If the SEL bit is reset, then
values below 16 will be forced to decimal 16 and values
greater than 235 will be forced to 235.
When the BYPASS bit is reset decimal 128 will be added
to each chrominance channel, to provide a positive only
number. The SEL bit then either limits the range to 1 to 254 or
to 16 to 240. Values outside those ranges are respectively
forced to the minimum or maximum values. Note that if the
BYPASS pin is reset then the NORM bit must be set.
HOST INTERFACING
The VP510 utilizes a conventional microprocessor inter-
face except that the RAM based look up tables are not directly
addressable. The address inputs must meet set up and hold
times with respect to the front edge of the read and write
strobes. These are given in Figure 9. Note that the address
inputs are internally latched, and need not stay valid for the
whole of the strobe times. Chip select, however, must stay
active for the whole of the strobe times.
Data, which is to be written to the RAM or Control Register,
must meet set up and hold times with respect to the back edge
of the write strobe. These are also given in Figure 9. The
device clock must be present for the write operation to occur,
and internal synchronization takes place. For this reason the
write strobe must be active for at least 2 clock periods.
Reading data from the VP510 also requires the presence
of the device clock. Data from the RAM is internally pipelined
and the read strobe must be active for at least 5 clock periods
( 4 pipeline delays plus synchronization ). The output bus will
not go low impedance before this pipeline delay.
The matrix coefficients and the Control Register are di-
rectly addressable, and use the locations given in Table 1.
Four addresses are used to access the three RAM's, and the
scheme used is descibed in the section on the look up tables.
DEVICE CONFIGURATION
The device is configured by means of bits in a Control
Register. A reset pulse must be applied, whilst the device
clock is active, before loading the Control Register. The reset
pulse will actually clear all the control bits to zero, and ensure
that neither output bus is low impedance, even if OEN is low.
The significance of the bits is given below. For a fuller
description of individual bits see the releant sections.
BIT NAME
FUNCTION
0
OEI
This bit must be set and the OEN pin must be
low for either the 24 or 16 bit output bus to be
low impedance. The status of the MODE bit
determines which bus is actually enabled as an
output. With this arrangement either bus can
be controlled by software or by driving a pin.
1
SEL
This bit controls the range of the luminance and
chrominance data. When high the I/O range is
1-254. When low the luminance is 16-235 and
the chrominance is 16-240.
2
MODE
This bit selects the direction of operation. When
low the 24 bit bus represents RGB inputs and
the 16 bit bus represents luminance and
chrominance outputs. The filters then deci
mate. When high the data flow reverses and the
filters interpolate.
ADDR
FUNCTION
ADDR
FUNCTION
0
2
4
6
8
10
12
14
16
27
28
29
30
31
18 - 26
C1 L Byte
C2 L Byte
C3 L Byte
C4 L Byte
C5 L Byte
C6 L Byte
C7 L Byte
C8 L Byte
C9 L Byte
RAM Address Reset
R/W Red RAM
R/W Green RAM
R/W Blue RAM
Control Register
Not Used
1
3
5
7
9
11
13
15
17
C1 H Byte
C2 H Byte
C3 H Byte
C4 H Byte
C5 H Byte
C6 H Byte
C7 H Byte
C8 H Byte
C9 H Byte
Table 1. Internal Address Map
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP520CGGGWR | Video Converter Circuit |
| VP520CGGH1R | Video Converter Circuit |
| VP520SCGGH1R | PAL/NTSC to CIF/QCIF Converter |
| VP520SCG | PAL/NTSC to CIF/QCIF Converter |
| VP520S | PAL/NTSC to CIF/QCIF Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP511 | 制造商:Platt Luggage 功能描述:Vacuum Pack |
| VP5-1200 | 制造商:COOPER BUSSMANN 功能描述:Ind General Purpose 76.8uH 30% Ferrite 2.08A Bulk |
| VP5-1200-R | 功能描述:固定電感器 76.8uH 0.2A 0.047ohms RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
| VP5-1200TR | 制造商:COOPER BUSSMANN 功能描述:Ind Power Wirewound 76.8uH 30% Ferrite 2.08A T/R |
| VP5-1200TR-R | 功能描述:固定電感器 76.8uH 0.2A 0.047ohms RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
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