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參數(shù)資料
| 型號： | VP510CGGPFR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Bi Directional Colour Space Converter |
| 中文描述： | 8-BIT, DSP-VIDEO IMAGING, PQCC100 |
| 封裝： | PLASTIC, LCC-100 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 312K |
| 代理商： | VP510CGGPFR |
VP 510
6
adjusted to have a range of 16 - 235, and the Cr and Cb inputs
will be adjusted to 16 - 240. If the SEL bit is set the range will
be 1 - 254 for all three inputs. After either ranging option 128
is subtracted from the Cr and Cb channels before they are
applied to the matrix converter. Note that if the incoming Y Cr
Cb data is already correctly ranged then the range circuit will
have no further action. The BYPASS pin must, however, still
be reset or the offset of 128 will not be subtracted from the
chrominance channels.
RGB OUTPUTS
RGB outputs will be valid after the delay from the rising
edge of the clock given in Figure 6. A version of the HREF input
is provided ( HDLY ), which has been delayed by the same
number of clock periods as the data. This indicates when the
first converted samples are available from each line.
In normal operation of the VP510 the clock input will be two
times the sampling clock required to produce a given number
of pixels per line. The device then produces RGB outputs at
this double rate, and thus avoids the needed for analog anti
aliasing filters after the D/A converters. Incoming luminance
data is interpolated by two, and chrominance data by four, to
achieve these output rates.
For standard CCIR601 video with 720 RGB pixels per line
the clock needed would thus be 27 MHz. For square pixel
NTSC a clock of 24.54 is needed, and square pixel PAL needs
a clock of 29.5 MHz.
If the RGB outputs are connected to a frame store rather
than driving a D/A converter, then these oversampled outputs
are probably not needed. Since the RGB data will not contain
any frequencies above one quarter the clock rate used by the
VP510, then the user can simply just use every other output
sample without causing aliasing effects.
Each 8 bit output value is obtained from the output of the
matrix converter, which is internally represented by 13 bits.
This comprises 10 signed integer bits plus three fractional
bits. At this point the RGB values have a range of -512 to +511,
which is sufficient to accommodate any overshoot or under-
shoot produced by the filters. If the most significant fractional
bit is set, then the integer bits are incremented by one, and the
result is then clipped. Negative values will be forced to zero,
and values greater than +255 will be forced to saturate at
+255. The resulting unsigned 8 bit number is made available
on the output pins, as shown in Figure 2.
LUMINANCE AND CHROMINANCE
OUTPUTS
The 16 bit output bus changes on alternate rising edges of
the clock, with the delay specified in Figure 7. Each output
remains valid for two clock periods and is either comprised of
a luminance byte plus a U, I, or Cr component, or another
luminance byte plus a V, Q, or Cb component. The sequence
of events following the HREF delayed output is shown in
Figure 7. The CRO signal can be used as a clock enable or
a half rate clock for the next component in the system.
Figure 8. Chrominance and Luminance Output Options
Figure 9. Host Interface Timing (Advanced Data)
ADD
8 BIT CLIPPED
INPUT ( ±128 )
128
RANGE
16-240
RANGE
1-254
BYPASS
SEL
CHROMINANCE OUTPUTS
8 BIT CLIPPED
INPUT ( 0 - 255 )
RANGE
16-235
RANGE
1-254
BYPASS
SEL
LUMINANCE OUTPUT
MIN
10ns
10ns
0ns
0ns
3
ns
2
ns
10ns
10ns
SYMBOL
Tas
Tah
Tws
Tsh
Twi
Twa
Tds
Tdh
CHARACTERISTIC
Addresss Set Up Time
Address Hold Time
Chip Select Set Up Time
Chip Select Hold Time
Strobe In active Time
Strobe Active Time
Data Set Up Time
Data Hold Time
MAX
10 +5
ns
25ns
SYMBOL
Tas
Tah
Trs
Tsh
Tri
Tac
Tlz
Thz
Trs
Data Valid
Tri
Tac
Tas
Tah
Thz
Tlz
Tsh
ADDRESS
CHIP
SELECT
READ
STROBE
DATA
OUT
Tws
Data Valid
Twi
Tds
T
Tah
ADDRESS
CHIP
SELECT
WRITE
STROBE
DATA
IN
WRITE CYCLE
READ CYCLE
CHARACTERISTIC
Addresss Set Up Time
Address Hold Time
Chip Select Set Up Time
Chip Select Hold Time
Strobe In active Time
Data Access Time
Delay to O/P's low Z
Delay to O/P's high Z
NOTE
is the period of the
input clock
MIN
10ns
10ns
0ns
0ns
ns
4
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP520CGGGWR | Video Converter Circuit |
| VP520CGGH1R | Video Converter Circuit |
| VP520SCGGH1R | PAL/NTSC to CIF/QCIF Converter |
| VP520SCG | PAL/NTSC to CIF/QCIF Converter |
| VP520S | PAL/NTSC to CIF/QCIF Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP511 | 制造商:Platt Luggage 功能描述:Vacuum Pack |
| VP5-1200 | 制造商:COOPER BUSSMANN 功能描述:Ind General Purpose 76.8uH 30% Ferrite 2.08A Bulk |
| VP5-1200-R | 功能描述:固定電感器 76.8uH 0.2A 0.047ohms RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
| VP5-1200TR | 制造商:COOPER BUSSMANN 功能描述:Ind Power Wirewound 76.8uH 30% Ferrite 2.08A T/R |
| VP5-1200TR-R | 功能描述:固定電感器 76.8uH 0.2A 0.047ohms RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm |
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