參數(shù)資料
型號(hào)： VES1848
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Single Chip DAVIC/DVB-RC Cable Modem(單片DAVIC/DVB-RC電纜調(diào)制解調(diào)器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP208
封裝： MQFP-208
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 122K
代理商： VES1848
1999 Jul 01
13
Philips Semiconductors
Product specification
Single Chip DAVIC/DVB-RC Cable Modem
VES1848
SYMBOL
RESET
PIN NUMBER
75
TYPE
I
DESCRIPTION
The RESET input is asynchronous, active low, and clears the VES
1848. When RESET goes low, the circuit immediately enters its
reset mode and normal operation will resume 4 OOB_clk falling
edges or 8 US_clk falling edges or 4 IBclk falling edges (depending
which delay is the bigger) later after RESET returned high. The
register contents are all initialized to their default values. The
minimum width of RESET at low level is the maximum of 4 OOB_clk
clock periods, 8 US_clk clock periods and 4 IBclk clock periods.
Controls the working frequency of the interface block.
If Fsysus > 65MHz then Fmicro must be set to Vdd.
If Fsysus
≤
65MHz then Fmicro must be set to Vss.
If a single micro-processor is used to read the MAC data and the
application layers data then nb_micro must be set to Vdd.
If the application layers data are read by an other circuit then
nb_micro must be set to Vss.
Must be set to Vss.
Application layers data can only be read through a micro processor
interface.
MAC interface address bus.
AddM[7] is the MSB.
MAC interface data bus.
DataM[7] is the MSB.
MAC interface active low interrupt line.
IntM is an open drain output and therefore requires an external pull
up resistor to VCC.
Host interface STRobe mode (Intel=0, Motorola=1) for the MAC
interface.
Host interface MUX mode for the MAC interface : address and data
multiplexed (=1) or not (=0).
MAC interface active low read strobe (Intel mode) or active low data
valid (Motorola mode).
MAC interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
MAC interface active low Chip Select.
MAC interface Address Latch Enable (only for multiplexed micro-
processor).
Application layers interface address bus.
addA[4] is the MSB.
Application layers interface data bus.
dataA[15] is the MSB.
Fmicro
37
I
nb_micro
36
I
utopia
33
I
AddM[7:0]
9,10,11,12
13,16,17,18
19,20,21,22
23,26,27,28
6
I
DataM[7:0]
I/O
(5V)
O
(5V)
IntM
hstbmodeM
32
I
hmuxmodeM
31
I
rdn_enaM
8
I
wrnM
7
I
csM
aleM
29
30
I
I
addA[4:0]
189,190,191
192,193
194,195,196,197
198,199,200,201
202,203,204,205
206,207,208,1
182
I
dataA[15:0]
I/O
(5V)
IntA
O
(5V)
Application layers interface active low interrupt line.
IntA is an open drain output and therefore requires an external pull
up resistor to VCC.
Host interface STRobe mode (Intel=0, Motorola=1) for the
application layers interface.
Host interface MUX mode for the application layers interface :
address and data multiplexed (=1) or not (=0).
application layers interface active low read strobe (Intel mode) or
active low data valid (Motorola mode).
application layers interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
application layers interface active low Chip Select.
hstbmodeA
3
I
hmuxmodeA
2
I
rdn_enaA
184
I
wrnA
183
I
csA
186
I
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VES-220M1ETR-0605 功能描述:鋁質(zhì)電解電容器-SMD 25 Volts 22uF 20% 6.3x5.3 RoHS:否 制造商:Vishay/BC Components 電容:2200 uF 容差:20 % 電壓額定值:16 V ESR: 工作溫度范圍:- 55 C to + 150 C 尺寸:16 mm W x 16 mm L x 21 mm H 產(chǎn)品:High Temp Electrolytic Capacitors
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