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參數(shù)資料
| 型號： | VES1848 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Chip DAVIC/DVB-RC Cable Modem(單片DAVIC/DVB-RC電纜調(diào)制解調(diào)器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP208 |
| 封裝： | MQFP-208 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 122K |
| 代理商： | VES1848 |
1999 Jul 01
11
Philips Semiconductors
Product specification
Single Chip DAVIC/DVB-RC Cable Modem
VES1848
2 INPUT - OUTPUT SIGNAL DESCRIPTION
SYMBOL
US_clk_in
PIN NUMBER
173
TYPE
I
DESCRIPTION
XTAL oscillator input pin. Typically a fifth overtone XTAL oscillator is
connected between the US_clk_in and US_clk_out pins.
XTAL oscillator output pin. Typically a fifth overtone XTAL oscillator
is connected between the US_clk_in and US_clk_out pins.
XTAL oscillator input pin. Typically a fifth overtone XTAL oscillator is
connected between the OOB_clk_in and OOB_clk_out pins.
XTAL oscillator output pin. Typically a fifth overtone XTAL oscillator
is connected between the OOB_clk_in and OOB_clk_out pins.
IF digital OOB signal. OOB_dig[6:0] is connected to an external A/D
converter. OOB_dig[6] is the MSB. When not used, OOB_dig[6 :0]
must be tied to ground.
IF OOB Sampling ClocK. Can be used as the sampling clock of an
external 7-bit ADC that will generate OOB_dig signals.
Output of the OOB DQPSK demodulator. Data are output on the
falling edge of clk_oob.
Bit clock associated with Doob.
US_clk_out
174
O
OOB_clk_in
78
I
OOB_clk_out
79
O
OOB_dig[6:0]
86,87,88,89
90,91,92
I
OOB_saclk
85
O
(5V)
O
(5V)
O
(5V)
O
(5V)
O
(5V)
Doob
54
clk_oob
55
VAGC
82
PWM encoded output signal for AGC. This signal is typically fed to
the AGC amplifier through a single RC network.
PWM encoded programmable signal. The encoded data is the
parameter PWM2 (C2[7-0]). This signal can be used to control a
second input of the AGC amplifier through a single RC network.
IB symbol clock. This clock is provided by the QAM demodulator.
Its polarity can be selected with parameter PsymbIB(AE.3).
IB byte clock associated with the data bus IB[7:0].
Its polarity can be selected with parameter PbyteIB(AE.2).
IB MPEG2-TS input. These 8-bit parallel data are the outputs of the
DS QAM FEC.
When the parallel interface is selected (Parameter serie = 0,
address 82.6) then IB[7:0] is the transport stream input (IB[7] is the
MSB).
When the serial interface is selected (Parameter serie = 1, address
82.6) then the serial input is on pin IB[0] (pin 41).
If parameter Ps_DE=0
(address 83.7) : Pulse SYNChro. This input
signal must be high when the sync byte (47
16
) is provided on IB[7:0],
then it must be low until the next sync byte. If the serial interface is
selected, then PSYNC is high only during the first bit of the sync
byte (47
16
).
If parameter Ps_DE=1
(address 83.7) : data enable. This input
signal must be high during the first 188 bytes of the MPEG2-TS
packet. It is then low during the redondancy bytes.
EXTernal SYNChro. Only used when parameter InExt=1 (88.1).
When not used, must be tied to ground.
This input signal toggles at each US burst start.
EXT_SYNC must be initiated to 0.
Programmable clock with the parameter contiCk (AF.[5-4]). This
clock must be used in continuous mode to generate Iconti[2:0] and
Qconti[2:0].
I input for the US modulator in continuous mode (parameter
contiMode=1 (AF.3), and contiMem=0 (AF.6)). This data bus is
clocked on the rising edge of Fconti clock.
PWM2
81
IBsymbclk
38
I
IBclk
39
I
IB[7:0]
41,42,45,46
47,48,49,50
I
PSYNC
40
I
EXT_SYNC
93
I
Fconti
94
O
(5V)
Iconti[2:0]
98,99,100
I
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