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參數(shù)資料
| 型號(hào)： | VDS8616A8A |
| 廠商： | ADATA Technology Co., Ltd. |
| 英文描述： | Synchronous DRAM(4M X 16 Bit X 4 Banks) |
| 中文描述： | 同步DRAM（4米× 16位× 4個(gè)銀行） |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 538K |
| 代理商： | VDS8616A8A |
V-Data
VDS8616A8A
Pin Description
PIN
NAME
FUNCTION
CK
System Clock
Active on the positive edge to sample all inputs.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
A0~A12
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A8
BS0~BS1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ16 Data
Data inputs / outputs are multiplexed on the same pins.
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
DQM
Mode
Register
C
C
R
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank1
Bank3
Amplifier
Column Decoder
Data Control Circuit
D
DQ0~DQn
DQS
Rev 1.0 December, 2001
2
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