參數(shù)資料
型號(hào): VDS8616A8A-75A
廠商: ADATA Technology Co., Ltd.
英文描述: Synchronous DRAM(4M X 16 Bit X 4 Banks)
中文描述: 同步DRAM(4米× 16位× 4個(gè)銀行)
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 538K
代理商: VDS8616A8A-75A
V-Data
VDS8616A8A
AC Characteristics
Speed
75
75A
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
/CAS Latency = 2 tCK2
7.5
1000
10
7.5
System clock
Cycle time
/CAS Latency = 3 tCK3
7
1000
7.5
7
ns
Clock high pulse width
tCHW
2.5
2.5
ns
1
Clock low pulse width
tCLW
2.5
2.5
ns
1
/CAS Latency = 2 tAC2
5.4
6
Access time form
clock
/CAS Latency = 3 tAC3
5.4
5.4
ns
2
/CAS Latency = 2 tWR2
7.5
10
7.5
Write Recovery
Time
/CAS Latency = 3 tWR3
7
7.5
7
/RAS cycle time
tRC
56
65
ns
/RAS to /CAS delay
tRCD
15
20
ns
/RAS active time
tRAS
40
100K
45
100K
ns
/RAS precharge time
tRP
15
20
ns
/RAS to /RAS bank active delay
tRRD
15
15
ns
/CAS to /CAS delay
tCCD
1
1
CLK
Data – input setup time
tDS
1.5
1.5
ns
1
Data – input hold time
tDH
0.8
0.8
ns
1
Address setup time
tAS
1.5
1.5
ns
1
Address hold time
tAH
0.8
0.8
ns
1
CKE setup time
tCKS
1.5
1.5
ns
1
CKE hold time
tCKH
0.8
0.8
ns
1
Command setup time
tCMS
1.5
1.5
ns
1
Command hold time
tCMH
0.8
0.8
ns
1
Output Data Hold Time
tOH
3
3
ns
Output Data High Impedance Time
tHZ
3
7
3
7.5
ns
Output Data Low Impedance Time
tLZ
0
0
ns
Mode register Set Cycle Time
tRSC
14
15
ns
Refresh time
tREF
64
64
ms
Note :
1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 December, 2001
6
相關(guān)PDF資料
PDF描述
VDS8616A8A Synchronous DRAM(4M X 16 Bit X 4 Banks)
VDS8616A8A-75 Synchronous DRAM(4M X 16 Bit X 4 Banks)
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