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參數(shù)資料
| 型號(hào)： | V62C51864L-35PI |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 8K X 8 STATIC RAM |
| 中文描述： | 8K的× 8靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 59K |
| 代理商： | V62C51864L-35PI |
2
V62C51864 Rev. 2.1 June 1998
MOSEL V ITELIC
V62C51864
Pin Descriptions
A
These 13 address inputs select one of the 8,192 x
8-bit words in the RAM.
0
–A
12
Address Inputs
CE
CE
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
1
1
, CE
is active LOW and CE
2
Chip Enable Inputs
2
is active HIGH. Both
OE
The Output Enable input is active LOW. When OE
is LOW with CE
1
LOW, CE
data of the selected memory location will be
available on the I/O pins. When OE is HIGH, the I/O
pins will be in the high impedance state.
Output Enable Input
2
HIGH, and WE HIGH,
WE
An active LOW input, WE input controls read and
write operations. When CE
both LOW with CE
2
HIGH, the data present on the
I/O pins will be written into the selected memory
location.
Write Enable Input
1
and WE inputs are
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
7
Data Input/Output Ports
V
CC
Power Supply
GND
Ground
Pin Configuration
28-Pin Plastic DIP/SOP
Top View
V
CC
A
8
A
9
A
11
OE
A
10
I/O
0
I/O
1
I/O
2
GND
A
0
A
1
A
2
A
3
A
4
A
5
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
51864 02
CE
2
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A
12
A
6
A
7
CE
1
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