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參數(shù)資料
| 型號(hào)： | V62C31864 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 2.7 VOLT 8K X 8 STATIC RAM |
| 中文描述： | 2.7伏8K的× 8靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | V62C31864 |
2
V62C31864 Rev. 1.6 August 1998
MOSEL V ITELIC
V62C31864
Pin Descriptions
A
These 13 address inputs select one of the 8,192 x 8
bit segments in the RAM.
0
–A
12
Address Inputs
CE
CE
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
1
1
, CE
is active LOW and CE
2
Chip Enable Inputs
2
is active HIGH. Both
OE
The Output Enable input is active LOW. When OE
is LOW with CE
1
LOW, CE
data of the selected memory location will be
available on the I/O pins. When OE is HIGH, the I/O
pins will be in the high impedance state.
Output Enable Input
2
HIGH, and WE HIGH,
WE
An active LOW input, WE input controls read and
write operations. When CE
both LOW with CE
2
HIGH, the data present on the
I/O pins will be written into the selected memory
location.
Write Enable Input
1
and WE inputs are
I/O
These 8 bidirectional ports are used to read data
from and write data into the RAM.
0
–I/O
7
Data Input and Data Output Ports
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
28-Pin SOP
28-Pin TSOP (Standard)
V
CC
A
8
A
9
A
11
OE
A
10
I/O
0
I/O
1
I/O
2
GND
A
0
A
1
A
2
A
3
A
4
A
5
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
51864 02
CE
2
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A
12
A
6
A
7
CE
1
OE
A11
A9
A8
CE2
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
51864 03
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