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參數(shù)資料
| 型號(hào)： | V62C1884096LL-85BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 85 ns, PBGA36 |
| 封裝： | 8 X 10 MM, CSP, BGA-36 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 48K |
| 代理商： | V62C1884096LL-85BI |
2
V62C1884096 Rev. 1.2 June 2000
MOSEL VITELIC
V62C1884096
Pin Descriptions
A0–A18
Address Inputs
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O1–I/O8 Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
VCC
Power Supply
GND
Ground
Pin Configurations (Top View)
36 BGA
A
1
234
56
1
Note: NC means no connect.
NB means no ball.
2
TOP VIEW
34
5
6
B
C
D
E
F
G
H
A
A0
I/O5
I/O6
B
C
D
E
F
G
H
VSS
VCC
I/O7
I/O8
A9
A1
A2
NB
OE
A10
CE2
WE
NC
NB
A18
CE1
A11
A3
A4
A5
NB
A17
A16
A12
A6
A7
NB
A15
A13
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
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