參數(shù)資料
型號(hào): V62C18164096L
廠商: Mosel Vitelic, Corp.
英文描述: 256K x 16, CMOS STATIC RAM
中文描述: 256K × 16,的CMOS靜態(tài)RAM
文件頁數(shù): 6/10頁
文件大小: 51K
代理商: V62C18164096L
6
V62C18164096 Rev. 1.2 June 2000
MOSEL V ITELIC
V62C18164096
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Write Cycle
Parameter
Name
Parameter
85
100
Unit
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
85
70
ns
t
AA
Address Access Time
85
100
ns
t
ACS
Chip Enable Access Time
85
100
ns
t
BA
UBE, LBE Access Time
85
100
ns
t
OE
Output Enable to Output Valid
35
40
ns
t
CLZ
Chip Enable to Output in Low Z
10
15
ns
t
BLZ
UBE, LBE to Output in Low Z
10
15
ns
t
OLZ
Output Enable to Output in Low Z
10
10
ns
t
CHZ
Chip Disable to Output in High Z
0
30
0
35
ns
t
OHZ
Output Disable to Output in High Z
0
30
0
35
ns
t
BHZ
UBE, LBE to Output in High Z
0
30
0
35
ns
t
OH
Output Hold from Address Change
10
10
ns
Parameter
Name
Parameter
85
100
Unit
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
85
100
ns
t
CW
Chip Enable to End of Write
70
80
ns
t
AS
Address Setup Time
0
0
ns
t
AW
Address Valid to End of Write
70
80
ns
t
WP
Write Pulse Width
60
70
ns
t
WR
Write Recovery Time
0
0
ns
t
WHZ
Write to Output High-Z
0
25
0
35
ns
t
DW
Data Setup to End of Write
40
45
ns
t
DH
Data Hold from End of Write
0
0
ns
t
BW
UBE, LBE to End of Write
70
80
ns
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