- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297706 > V62/09616-01XE (TEXAS INSTRUMENTS INC) 4-CHANNEL, SGL ENDED MULTIPLEXER, PDSO14 PDF資料下載
參數(shù)資料
| 型號： | V62/09616-01XE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 多路復用及模擬開關(guān) |
| 英文描述： | 4-CHANNEL, SGL ENDED MULTIPLEXER, PDSO14 |
| 封裝： | PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大小： | 860K |
| 代理商： | V62/09616-01XE |
DRIVING CAPACITIVE LOADS
V
=V
(R
I )
G
OSO_envelope
OS
S
b
G
I xR
bi
F
±
±- -
5
(V )
10
S
-
PSRR
-
20
± -
5
(V )
10
S+
-
PSRR+
20
(7)
±- - -
5
( 6)
10
-
51
20
50
20
± -
5
6
10
-
= 29.2mV
±
+523
18 A
W ± m
±
±
10mV+75
14 A
2
W
m
(8)
DISTORTION PERFORMANCE
DC ACCURACY
SBOS444 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
One of the most demanding, yet very common load
conditions, is capacitive loading. Often, the capacitive
load is the input of an analog-to-digital converter
(ADC)—including additional external capacitance that
Where:
may be recommended to improve ADC linearity. A
RS: Input resistance seen by R0, R1, G0, G1, B0,
high-speed device such as the OPA4872 can be very
or B1.
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
Ib: Noninverting input bias current
directly on the output pin. When the device open-loop
Ibi: Inverting input bias current
output resistance is considered, this capacitive load
G: Gain
introduces an additional pole in the signal path that
VS+: Positive supply voltage
can decrease the phase margin. Several external
solutions to this problem have been suggested. When
VS–: Negative supply voltage
the primary considerations are frequency response
PSRR+: Positive supply PSRR
flatness, pulse response fidelity, and/or distortion, the
PSRR–: Negative supply PSRR
simplest and most effective solution is to isolate the
VOS: Input Offset Voltage
capacitive load from the feedback loop by inserting a
series isolation resistor between the amplifier output
Evaluating
the
front-page
schematic,
using
a
and the capacitive load. This isolation resistor does
worst-case, +25°C offset voltage, bias current and
not eliminate the pole from the loop response, but
PSRR specifications and operating at ±6 V, gives a
rather shifts it and adds a zero at a higher frequency.
worst-case output equal to Equation 8:
The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting frequency
response at the load; see Figure 5. Parasitic
capacitive loads greater than 2 pF can begin to
degrade the performance of the OPA4872. Long PCB
The OPA4872 provides good distortion performance
traces,
unmatched
cables,
and
connections
to
into a 150-
load on ±5-V supplies. Relative to
multiple devices can easily cause this value to be
alternative
solutions,
it
provides
exceptional
exceeded. Always consider this effect carefully, and
performance into lighter loads. Generally, until the
add the recommended series resistor as close as
fundamental signal reaches very high frequency or
possible to the OPA4872 output pin (see the Board
power levels, the 2nd harmonic dominates the
Layout Guidelines section).
distortion with a negligible 3rd harmonic component.
Focusing then on the 2nd harmonic, increasing the
load impedance directly improves distortion. Also,
The OPA4872 offers excellent dc signal accuracy.
providing an additional supply decoupling capacitor
Parameters that influence the output dc offset voltage
(0.01
F) between the supply pins (for bipolar
are:
operation) improves the 2nd-order distortion slightly
Output offset voltage
(3 dB to 6 dB).
Input bias current
In most op amps, increasing the output voltage swing
Gain error
increases harmonic distortion directly. The Typical
Power-supply rejection ratio
Characteristics show the 2nd harmonic increasing at
a little less than the expected 2X rate while the 3rd
Temperature
harmonic increases at a little less than the expected
3X rate. Where the test power doubles, the 2nd
Leaving both temperature and gain error parameters
harmonic increases only by less than the expected 6
aside, the output offset voltage envelope can be
dB, whereas the 3rd harmonic increases by less than
described as shown in Equation 7:
the expected 12 dB.
16
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4872-EP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V62C31162048LL-70KI | 128K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| V6300ETO-92 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBCY3 |
| V6300KSOT-23 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| V6300GTO-92 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBCY3 |
| V6300BSOT-23 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V62-09620-01XA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLER |
| V620H011M | 制造商:OMRON Industrial Automation 功能描述: 制造商:Omron Corporation 功能描述: |
| V620H015M | 制造商:OMRON Industrial Automation 功能描述: |
| V620H025M | 制造商:OMRON Industrial Automation 功能描述: 制造商:Omron Corporation 功能描述: |
| V620TE01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VOLTAGE CONTROLLED OSCILLATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。