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ABSOLUTE MAXIMUM RATINGS
(1)
PIN CONFIGURATION
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SD
EN
A1
IN0
GND
IN2
V-
IN1
IN3
V+
OUT
FB
A0
GND
Logic
OPA4872
www.ti.com........................................................................................................................................................................................... SBOS444 – DECEMBER 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PACKAGE-LEAD
DESIGNATOR(2)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
SO-14
D
–55°C to 125°C
OPA4872M
OPA4872MDREP
Tape and Reel, 2500
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Over operating free-air temperature range, unless otherwise noted.
OPA4872
UNIT
Power supply
±6.5
V
Internal power dissipation
See Thermal Characteristics
Input voltage range
±VS
V
Storage temperature range
–65 to +125
°C
Lead temperature (soldering, 10s)
+260
°C
Junction temperature (TJ)
+150
°C
Junction temperature: continuous operation, long-term reliability
+140
°C
Human body model (HBM)
1500
V
ESD rating
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
SO-14
Top View
Copyright 2008, Texas Instruments Incorporated
3