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參數(shù)資料
| 型號(hào)： | V59C1G01168QBLJ-25I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA84 |
| 封裝： | GREEN, FBGA-84 |
| 文件頁(yè)數(shù)： | 3/82頁(yè) |
| 文件大小： | 995K |
| 代理商： | V59C1G01168QBLJ-25I |
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11
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QB
V59C1G01(408/808/168)QB Rev. 1.1 December 2008
DDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT
value selection and additive latency. The default value of the extended mode register is not defined, therefore
the extended mode register must be written after power-up for proper operation Extended mode register(1)
.
is written by asserting low on CS, RAS, CAS, WE and high on BA0 and low on BA1, and controlling rest of
pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to com-
plete the write operation to the extended mode register. Mode register contents can be changed using the
same command and clock cycle requirements during normal operation as long as all banks are in the pre-
charge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output drive
A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for
OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time
the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn-
chronization to occur may result in a violation of the tAC or tDQSCK parameters.
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