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| 型號： | V58C2256324SHUZ5I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, PBGA60 |
| 封裝： | M0-233, FBGA-60 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 1125K |
| 代理商： | V58C2256324SHUZ5I |
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48
V58C2256(804/404/164)SH Rev. 1.1 July 2010
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
Figure 38 - INITIALIZE AND MODE REGISTER SETS
CKE
LVCMOS LOW LEVEL
DQ
BA0, BA1
200 cycles of CLK**
Extended
Mode
Register
Set
Load
Mode
Register,
Reset DLL
(with A8 = H)
Load
Mode
Register
(with A8 = L)
tMRD
tRP
tRFC
t IS
Power-up:
VDD and
CLK stable
T = 200
μs
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tIH
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DQS
High-Z
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A0-A9, A11
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A10
ALL BANKS
DON'T CARE
CK
/CK
tCK
tCH
tCL
VTT
(system*)
t VTD
VREF
VDD
VDDQ
COMMAND
MRS
NOP
PRE
EMRS
AR
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AR
tIS tIH
BA0=H,
BA1=L
tIS tIH
BA0=L,
BA1=L
tIS tIH
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CODE
tIS tIH
CODE
MRS
BA0=L,
BA1=L
CODE
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PRE
ALL BANKS
tIS tIH
RA
ACT
BA
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.
The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.
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CODE
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