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參數(shù)資料
| 型號(hào)： | V58C2256324SHUZ5I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, PBGA60 |
| 封裝： | M0-233, FBGA-60 |
| 文件頁數(shù)： | 1/60頁 |
| 文件大?。?/td> | 1125K |
| 代理商： | V58C2256324SHUZ5I |
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V58C2256(804/404/164)SH
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
V58C2256(804/404/164)SH Rev.1.1 July 2010
45
6
DDR500
DDR400
DDR333
Clock Cycle Time (tCK2)
5ns
7.5ns
Clock Cycle Time (tCK2.5)
5ns
6ns
Clock Cycle Time (tCK3)
4ns
5ns
6ns
System Frequency (fCK max)
250 MHz
200 MHz
166 MHz
Features
-
High speed data transfer rates with system
frequency up to 250 MHz
-
Data Mask for Write Control
-
Four Banks controlled by BA0 & BA1
-
Programmable CAS Latency: 2, 2.5, 3
-
Programmable Wrap Sequence: Sequential
or Interleave
-
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
-
Automatic and Controlled Precharge Command
-
Power Down Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval: 8192 cycles/64 ms
-
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
-
SSTL-2 Compatible I/Os
-
Double Data Rate (DDR)
-
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
-
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
-
Differential clock inputs CK and CK
-
Power Supply 2.5V ± 0.2V for all products
-
tRAS lockout supported
-
Concurrent auto precharge option is supported
Description
The V58C2256(804/404/164)SH is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SH achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the out-
put data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock.
I/O transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A
sequential and gapless data rate is possible depending
on burst length, CAS latency and speed grade of the
device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
60 FBGA
-4
-5
-6
Std.
L
0°C to 70°C
Blank
-40°C to 85°C
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C2256404SHLB6I | 64M X 4 DDR DRAM, PBGA60 |
| V58C2256404SHLM5I | 64M X 4 DDR DRAM, PBGA60 |
| V58C2256404SHLZ4E | 64M X 4 DDR DRAM, PBGA60 |
| V58C2256404SHUR5 | 64M X 4 DDR DRAM, PBGA60 |
| V58C2256804SHLI4I | 32M X 8 DDR DRAM, PDSO66 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C2256404S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804SAT-5 | 制造商:Mosel Vitelic Corporation 功能描述:SDRAM, DDR, 32M x 8, 66 Pin, Plastic, TSSOP |
| V58C265164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
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