參數(shù)資料
型號： V55C3256164VBUC8PC
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： SYNCHRONOUS DRAM, PBGA54
封裝： MO-210, FBGA-54
文件頁數(shù)： 46/46頁
文件大?。?/td> 575K
代理商： V55C3256164VBUC8PC
9
V55C3256164VB Rev. 1.0 March 2008
ProMOS TECHNOLOGIES
V55C3256164VB
A12 to A5
A3
A4
A2
A1
A0
Address Bus (Ax)
TCR
PASR
Mode Register
A4
A3
Max case temp
00
70OC
01
45OC
10
15OC
11
85OC
all have to be set to "0"
BA0
BA1
Partial-Array Self Refresh:
A2
A1
A0
banks to be self-refreshed
0
all banks
0
1
1/2 array (BA1=0)
0
1
0
1/4 array (BA1=0, BA0=0)
0
1
Reserved
1
0
Reserved
1
0
1
1/8 array (BA1=BA0=0, A11=0)
1
0
1/16 array (BA1=BA0=0,
A11=A10=0)
1
Reserved
1*)
0*)
Temperature-Compensated
Self-Refresh:
*)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register)
The Low Power Mode Register must be set during the initialization sequence. Once the device is operational, the
Low Power Mode Register set can be issued anytime when the part is idle.
Low Power Mode Register Table
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