參數(shù)資料
型號(hào)： V55C3256164VBUC8PC
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： SYNCHRONOUS DRAM, PBGA54
封裝： MO-210, FBGA-54
文件頁(yè)數(shù)： 43/46頁(yè)
文件大?。?/td> 575K
代理商： V55C3256164VBUC8PC
6
V55C3256164VB Rev. 1.0 March 2008
ProMOS TECHNOLOGIES
V55C3256164VB
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1.
V = Valid , x = Don’t Care, L = Low Level, H = High Level
2.
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3.
These are state of bank designated by BS0, BS1 signals.
4.
Power Down Mode can not entry in the burst cycle.
5. After Deep Power Down mode exit a full new initialization of memory device is mandatory
Operation
Device
State
CKE
n-1
CKE
nCS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Row Activate
Idle3
HX
L
H
X
V
Read
Active3
HX
LHLHX
V
L
V
Read w/Autoprecharge
Active3
HX
LHLHX
V
H
V
Write
Active3
HX
LHL
L
X
V
L
V
Write with Autoprecharge
Active3
HX
LHL
L
X
V
H
V
Row Precharge
Any
H
X
L
H
L
X
L
V
Precharge All
Any
H
X
L
H
L
X
H
X
Mode Register Set
Idle
H
X
L
X
V
No Operation
Any
H
X
L
H
X
Device Deselect
Any
H
X
H
X
Auto Refresh
Idle
H
L
H
X
Self Refresh Entry
Idle
H
L
H
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
XXX
XX
X
LH
H
X
Power Down Entry
Idle
Active4
HL
H
XXX
XX
X
LH
H
X
Power Down Exit
Any
(Power
Down)
LH
H
XXX
XX
X
LH
H
L
Data Write/Output Enable
Active
H
X
L
X
Data Write/Output Disable
Active
H
X
H
X
Deep Pwoer Down Entry
Idle
H
L
H
L
H
X
Deep Pwoer Down Exit
Deep power-
Down
L
H
X
XXX
H
X
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