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參數(shù)資料
| 型號： | V54C465164VEJ8PC |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| 封裝： | GREEN, FBGA-60 |
| 文件頁數(shù)： | 50/50頁 |
| 文件大?。?/td> | 628K |
| 代理商： | V54C465164VEJ8PC |
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V54C465164VE Rev. 1.4 May 2006
ProMOS TECHNOLOGIES
V54C465164VE
Address Input for Mode Set (Mode Register Operation)
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum tRAS or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially,
interleaved
bank
read
or
write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
A11
A3
A4
A2
A1
A0
A10 A9
A8
A7
A6
A5
Address Bus (Ax)
BT
Burst Length
CAS Latency
Mode Register
CAS Latency
A6
A5
A4
Latency
000
Reserve
001
Reserve
010
2
011
3
100
Reserve
101
Reserve
110
Reserve
111
Reserve
Burst Length
A2
A1
A0
Length
Sequential
Interleave
00
0
1
00
1
2
01
0
4
01
1
8
1
0
Reserve
1
0
1
Reserve
1
0
Reserve
1
Full Page
Reserve
Burst Type
A3
Type
0
Sequential
1
Interleave
Operation Mode
BA1 BA0 A11 A10 A9 A8 A7
Mode
000
0
Burst Read/Burst
Write
000
0
1
0
Burst Read/Single
Write
Operation Mode
BA0
BA1
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address
are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time
limits the number of random column accesses. A new burst access can be done even before the previous
burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted,
the remaining addresses are overridden by the new address with the full burst length. An interrupt which ac-
companies with an operation change from a read to a write is possible by exploiting DQM to avoid bus con-
tention.
When two or more
banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or more
banks can realize fast serial data access modes among many different pages. Once two or more banks are
activated, column to column interleave operation can be done between different pages.
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