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參數(shù)資料
| 型號(hào)： | V54C365804VD |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| 中文描述： | 高性能143/133/125 MHz的3.3伏8米× 8同步DRAM 4銀行X 2Mbit的× 8 |
| 文件頁數(shù)： | 1/54頁 |
| 文件大小： | 453K |
| 代理商： | V54C365804VD |
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MOSEL V ITELIC
1
V54C365804VC
HIGH PERFORMANCE 143/133/125 MHz
3.3 VOLT 8M X 8 SYNCHRONOUS DRAM
4 BANKS X 2Mbit X 8
V54C365804VC Rev. 0.6 September 1999
PRELIMINARY
7
75
8PC
8
System Frequency (f
CK
)
143MHz
133MHz
125 MHz
125 MHz
Clock Cycle Time (t
CK3
)
7 ns
7.5 ns
8 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
6 ns
7 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.5 ns
6 ns
6 ns
7 ns
Features
I
4 banks x 2Mbit x 8 organization
I
High speed data transfer rates up to 143 MHz
I
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I
Single Pulsed RAS Interface
I
Data Mask for Read/Write Control
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 3
I
Programmable Wrap Sequence: Sequential
or Interleave
I
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
I
Multiple Burst Read with Single Write Operation
I
Automatic and Controlled Precharge Command
I
Random Column Address every CLK (1-N Rule)
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 54 Pin 400 mil TSOP-II
I
LVTTL Interface
I
Single +3.3 V
±
0.3 V Power Supply
Description
The V54C365804VC is a four bank Synchronous
DRAM organized as 4 banks x 2Mbit x 8. The
V54C365804VC achieves high speed data transfer
rates up to 143 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
7
75
8PC
8
Std.
L
0
°
C to 70
°
C
Blank
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