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參數(shù)資料
| 型號(hào)： | V55C2128164VT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| 中文描述： | 128Mbit低功率SDRAM 2.5伏，第二的TSOP / BGA封裝，8米× 16 |
| 文件頁(yè)數(shù)： | 1/44頁(yè) |
| 文件大?。?/td> | 591K |
| 代理商： | V55C2128164VT |
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MOSEL VITELIC
1
V55C2128164V(T/B)
128Mbit LOW-POWER SDRAM
2.5 VOLT, TSOP II / BGA PACKAGE
8M X 16
V55C2128164V(T/B) Rev. 1.2 August 2002
PRELIMINARY
6
7PC
7
8PC
10
System Frequency (f
CK
)
166 MHz
143 MHz
143 MHz
125 MHz
100MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
7 ns
8 ns
10 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
7 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
8 ns
Clock Access Time (t
AC1
) CAS Latency = 1
19 ns
19 ns
19 ns
19 ns
22 ns
Features
■
4 banks x 2Mbit x 16 organization
■
High speed data transfer rates up to 166 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency:1, 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Power Down Mode and Clock Suspend Mode
■
Deep Power Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 4096 cycles/64 ms
■
Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 9x8 mm and 54 pin
TSOP II
■
VDD=2.5V, VDDQ=1.8V
■
■
Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■
Operating Temperature Range
Commercial (
0
°
C to 70
°
C)
Extended (-25
°
C to +85
°
C)
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Temperature
Mark
T/B
6
7PC
7
8PC
10
0
°
C to 70
°
C
Commercial
-25
°
C to 85
°
C
Extended
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