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參數(shù)資料
| 型號： | V54C3256 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| 中文描述： | 片256Mbit SDRAM的3.3伏，第二的TSOP /系統(tǒng)芯片的BGA / WBGA包裝16米x 16，32 × 8，64米× 4 |
| 文件頁數(shù)： | 1/52頁 |
| 文件大?。?/td> | 853K |
| 代理商： | V54C3256 |
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MOSEL VITELIC
1
V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC BGA / WBGA
PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
PRELIMINARY
6
7PC
7
8PC
System Frequency (f
CK
)
166 MHz
143 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
7 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
Features
■
4 banks x 4Mbit x 16 organization
■
4 banks x 8Mbit x 8 organization
■
4 banks x16Mbit x 4 organization
■
High speed data transfer rates up to 166 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC BGA
■
LVTTL Interface
■
Single +3.3 V
±
0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S/B
6
7PC
7
8PC
Std.
L
0
°
C to 70
°
C
Blank
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