參數(shù)資料
型號: V54C3256164VAT6
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 23/52頁
文件大?。?/td> 853K
代理商: V54C3256164VAT6
3
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A0–A12
Address Inputs
BA0, BA1
Bank Select
I/O1–I/O16
Data Input/Output
LDQM, UDQM
Data Mask
VCC
Power (+3.3V)
VSS
Ground
VCCQ
Power for I/O’s (+3.3V)
VSSQ
Ground for I/O’s
NC
Not connected
V 54 C 3 25616 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx16(8K Refresh)
4 Banks
V=LVTTL
Component Rev Level A=0.17um
Special
Feature
L=Low Power
TSOP Component
Package
Speed
6 ns
7 ns
8 ns
Device
Number
B=0.14um
Description
Pkg.
Pin Count
TSOP-II
T
54
VCC
I/O1
VCCQ
I/O2
I/O3
VSSQ
I/O4
I/O5
VCCQ
I/O6
I/O7
VSSQ
I/O8
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
VSS
I/O16
VSSQ
I/O15
I/O14
VCCQ
I/O13
I/O12
VSSQ
I/O11
I/O10
VCCQ
I/O9
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
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