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參數(shù)資料
| 型號(hào)： | V53C832L40 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 3.3 VOLT 256K X 32 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 高性能3.3伏256 × 32 EDO公司頁面模式的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 178K |
| 代理商： | V53C832L40 |
15
V53C832L Rev. 1.6 August 1999
MOSEL VITELIC
V53C832L
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
Don’t Care
Undefined
CAS0-CAS3
WE
OE
I/O
1
-I/O
32
ADDRESS
IH
V
V
IL
IH
V
V
IL
IH
V
V
IL
IH
V
V
IL
IH
V
V
IL
OH
V
V
OL
RAS
DVALID
832L-16
VALID
DATA OUT
AROW
COLUMN
COLUMN
COLUMN
VALID
t
RAS
t
CSH
t
CRP
t
RCD
t
CAS
t
CP
t
CP
t
CP
t
CAS
t
CAS
t
PC
t
AR
t
RAD
t
ASR
t
RAH
t
RCS
t
RCH
t
WCS
t
CAA
t
CAA
t
RAC
t
CAC
t
CAP
t
CAC
t
COH
t
DS
t
DH
t
OE
t
WCH
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAR
t
PC
t
RSH
t
RP
Functional Description
The V53C832L is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C832L reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address.
The V53C832L has four CAS inputs. CAS0 con-
trols I/O
1
–I/O
8
; CAS1 controls I/O
9
–I/O
16
; CAS2
controls I/O
17
–I/O
24
; and CAS3 controls I/O
23
–
I/O
32
. These four CAS inputs control Byte Read and
Byte Write.
The row address is latched by the Row Address
Strobe (RAS). The column address “flows through”
an internal address buffer and is latched by the
Column Address Strobe (CAS). Because access
time is primarily dependent on a valid column
address rather than the precise time that the CAS
edge occurs, the delay time from RAS to CAS has
little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum t
RAS
time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t
RP
/t
CP
has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by t
AR
. Data Out becomes valid
only when t
OAC
, t
RAC
, t
CAA
and t
CAC
are all satisifed.
As a result, the access time is dependent on the
timing relationships between these parameters. For
example, the access time is limited by t
CAA
when
t
RAC
, t
CAC
and t
OAC
are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS
low during a RAS operation. The column address is
latched by CAS. The Write Cycle can be WE con-
trolled or CAS controlled depending on whether WE
or CAS falls later. Consequently, the input data must
be valid at or before the falling edge of WE or CAS,
whichever occurs last. In the CAS-controlled Write
Cycle, when the leading edge of WE occurs prior to
the CAS low transition, the I/O data pins will be in the
High-Z state at the beginning of the Write function.
Ending the Write with RAS or CAS will maintain the
output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and t
OED
must be satisfied.
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