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參數(shù)資料
| 型號： | V53C8256H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Ultra-High Speed,256K x 8 Fast Page Mode CMOS Dynamic RAM(超高速256Kx8快速頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 超高速，256K × 8快速頁面模式的CMOS動態(tài)RAM（超高速256Kx8快速頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 147K |
| 代理商： | V53C8256H |
MOSEL V ITELIC
V53C8256H
15
V53C8256H Rev. 1.4 February 1999
Fast Page Mode provides a sustained data rate of
47 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Data Output Operation
The V53C8256H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(t
DS
) to be satisfied.
Power-On
After application of the V
DD
supply, an initial
pause of 200
μ
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
DD
current requirement of
the V53C8256H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and I
DD
will exhibit
current transients. It is recommended that RAS and
CAS track with V
DD
or be held at a valid V
IH
during
Power-On to avoid current surges.
Table 1. V53C8256H Data Output
Operation for Various Cycle Types
Data Rate
511
t
RC
t
PC
×
+
----------------------------------------
=
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read Cycle
Data from Addressed
Memory Cell
Fast Page Mode Write Cycle
(Early Write)
High-Z
Fast Page Mode Read-
Modify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
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