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參數(shù)資料
| 型號： | V53C819H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance 512K X 16 EDO Page Mode CMOS Dynamic RAM(高性能512Kx16EDO頁面模式動態(tài)RAM) |
| 中文描述： | 高性能EDO公司為512k × 16頁模式的CMOS動態(tài)RAM（高性能512Kx16EDO頁面模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 157K |
| 代理商： | V53C819H |
MOSEL V ITELIC
1
V53C819H
HIGH PERFORMANCE
512K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C819H Rev. 1.0 February 1999
HIGH PERFORMANCE
30
35
40
45
50
Max. RAS Access Time, (t
RAC
)
30 ns
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
16 ns
18 ns
20 ns
22 ns
24 ns
Min. Extended Data Out Mode Cycle Time, (t
PC
)
12 ns
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (t
RC
)
65 ns
70 ns
75 ns
80 ns
90 ns
Features
I
512K x 16-bit organization
I
EDO Page Mode for a sustained data rate of
83 MHz
I
RAS access time: 30, 35, 40, 45, 50 ns
I
Dual CAS Inputs
I
Pin-to-Pin compatible with 256K x 16
I
Low power dissipation
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
I
Refresh Interval: 1024 cycles/8 ms
I
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
I
Single +5V
±
10% Power Supply
I
TTL Interface
Description
The V53C819H is a 524,288 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C819H offers Page mode
operation with Extended Data Output. An address,
CAS and RAS input capacitances are reduced to
one half when the 256K x 16 DRAM is used to
construct
the
same
V53C819H has asymmetric address, 9-bit row and
10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
15ns.
The V53C819H is ideally suited for graphics,
digital signal processing and high performance
peripherals.
memory
density.
The
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
30
35
40
45
50
Std.
0
°
C to 70
°
C
Blank
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