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| 型號(hào)： | V53C365165AT50L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 EDO DRAM, 50 ns, PDSO50 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-50 |
| 文件頁(yè)數(shù)： | 26/26頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | V53C365165AT50L |
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V53C365165A Rev. 1.1 March 1998
MOSEL VITELIC
V53C365165A
15.
tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-
circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and
tCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.
These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-
Modify-Write cycles.
17)
When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
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