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參數資料
| 型號： | V53C365165AT50L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 EDO DRAM, 50 ns, PDSO50 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-50 |
| 文件頁數： | 25/26頁 |
| 文件大?。?/td> | 168K |
| 代理商： | V53C365165AT50L |
8
V53C365165A Rev. 1.1 March 1998
MOSEL VITELIC
V53C365165A
Notes:
1.
All voltages are referenced to VSS.
VIH may overshoot to VCC + 0.2V for pulse widths of < 4ns with 3.3V. VIL may undershoot to -2.0V for pulse width
< 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2.
ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3.
ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4.
Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a
hyper page mode cycle (tPC).
5.
An initial pause of 100
s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device
operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization
cycles instead of 8 RAS cycles are required.
6.
AC measurements assume tT = 2 ns.
7.
VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH and VIL.
8.
Measured with the specified current load and 100 pF at VOH = 2.0 V and VOL = 0.8 V.
9.
Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10.
Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11.
Either tRCH or tRRH must be satisfied for a read cycle.
12.
tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not
referenced to output voltage levels.
13.
Either tDZC or tDZO must be satisfied.
14.
Either tCDD or tODD must be satisfied.
CAS before RAS Refresh Cycle
56
tCSR
CAS setup time
5
—
5
—
5
—
ns
57
tCHR
CAS hold time
5
—
5
—
10
—
ns
58
tRPC
RAS to CAS precharge time
5
—
5
—
5
—
ns
59
tWRP
Write to RAS precharge time
5
—
5
—
10
—
ns
60
tWRH
Write hold time referenced to RAS
5
—
5
—
10
—
ns
Self Refresh Cycle (L-Version)
61
tRASS
RAS pulse width
100K
—
100K
—
100K
—
ns
17
62
tRPS
RAS precharge time
69
—
84
—
104
—
ns
17
63
tCHS
CAS hold time
50
—
50
—
50
—
ns
17
AC Characteristics (5,6) (Cont’d)
TA = 0 to 70°C,VCC = 3.3 V ±0.3V , tT = 2 ns
#
Symbol
Parameter
-40
- 50
- 60
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
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