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參數(shù)資料
| 型號(hào)： | V436632Z24VXTG-75PC |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 VOLT 32M x 64 HIGH PERFORMANCE 133 MHZ SDRAM UNBUFFERED SODIMM |
| 中文描述： | 3.3伏32M的× 64高性能133 MHz的內(nèi)存緩沖的SODIMM |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | V436632Z24VXTG-75PC |
MOSEL VITELIC
V436632Z24V
9
V436632Z24V Rev. 1.1 February 2002
Notes:
1.
The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2.
The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3.
All AC characteristics are shown for device level.
An initial pause of 100
s is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4.
AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5.
If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6.
Rated at 1.5V
7.
If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
8.
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
tDAL is equivalent to tDPL + tRP.
1.4V
tSETUP
tHOLD
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4V
0.4V
tT
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
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