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參數(shù)資料
| 型號： | V436632Z24VXTG-75PC |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 VOLT 32M x 64 HIGH PERFORMANCE 133 MHZ SDRAM UNBUFFERED SODIMM |
| 中文描述： | 3.3伏32M的× 64高性能133 MHz的內(nèi)存緩沖的SODIMM |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 297K |
| 代理商： | V436632Z24VXTG-75PC |
8
V436632Z24V Rev. 1.1 February 2002
MOSEL VITELIC
V436632Z24V
AC Characteristics 3,4
TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns
#
Symbol Parameter
Limit Values
Unit
Note
-75PC
-75
-10PC
Min.
Max.
Min.
Max.
Min.
Max.
Clock and Clock Enable
1tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
ns
2fCK
System frequency
CAS Latency = 3
CAS Latency = 2
–
133
–
133
100
–
100
MHz
3tAC
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
5.4
6
–
5.4
6
–
6
ns
4,5
4tCH
Clock High Pulse Width
2.5
–
2.5
–
3
–
ns
6
5tCL
Clock Low Pulse Width
2.5
–
2.5
–
3
–
ns
6
6tCS
Input Setup time
1.5
–
1.5
–
2
–
ns
7
7tCH
Input Hold Time
0.8
–
0.8
–
1
–
ns
7
8tCKSP
CKE Setup Time (Power down mode)
2.5
–
2.5
–
2
–
ns
8
9tCKSR
CKE Setup Time (Self Refresh Exit)
8
–
8
–
8
–
ns
9
10
tT
Transition time (rise and fall)
1
–
1
–
1
–
ns
Common Parameters
11
tRCD
RAS to CAS delay
20–20
–
20
–
ns
12
tRC
Cycle Time
70
120k
70
120k
70
120k
ns
13
tRAS
Active Command Period
42
–
45
–
45
–
ns
14
tRP
Precharge Time
15
–
20
–
20
–
ns
15
tRRD
Bank to Bank Delay Time
14
–
15
–
20
–
ns
16
tCCD
CAS to CAS delay time (same bank)
1–1
–1–
CLK
Refresh Cycle
17
tSREX
Self Refresh Exit Time
10
–
10
–
10
–ns
9
18
tREF
Refresh Period (8192 cycles)
64
–
64
–
64
–
ms
8
Read Cycle
19
tOH
Data Out Hold Time
3–3
–3–
ns
4
20
tLZ
Data Out to Low Impedance Time
0
–
0
–
0
–
ns
21
tHZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
8
ns
10
22
tDQZ
DQM Data Out Disable Latency
2
-
2
-
2
-
CLK
Write Cycle
23
tDPL
Data input to Precharge (write recovery)
2
–
2
–
1
–
CLK
24
tDAL
Data In to Active/refresh
5
–
5
–
5
–
CLK
11
25
tDQW
DQM Write Mask Latency
0–0
–0–
CLK
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