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參數(shù)資料
| 型號： | V370PDC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit |
| 中文描述： | 高性能PCI SDRAM控制器的集成了外圍控制單元 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 99K |
| 代理商： | V370PDC |
V370PDC
Copyright 1999, V3 Semiconductor Corp.
V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101
13
Notes:
1. Applies only to READY pin when i960_RDY bit in LB_BUS_CFG register is set to
’
1
’
.
Table 12: Local Bus Timing Parameters for Vcc =3.3 Volts +/- 5%
66MHz
#
Symbol
Description
Notes
Min
Max
Units
1
T
C
CLKIN period
15
ns
2
T
CH
CLKIN high time
5.5
ns
3
T
CL
CLKIN low time
5.5
ns
4
T
SU
Synchronous input setup
3
ns
4a
T
SU
Asynchronous input setup (READY)
1
7
ns
5
T
H
Synchronous input hold
1
ns
6
T
COV
CLKIN to output valid delay
3
11
ns
7
T
CZO
CLKIN to output driving delay
3
11
ns
8
T
COZ
CLKIN to high impedance delay
4
12
ns
9
T
ALE
ALE Pulse Width
T
CH
+0.5
T
CH
+1
ns
10
T
CLH
CLKIN rising to ALE rising
2
10
ns
11
T
AH
CLKIN falling to ALE falling
2
10
ns
Table 13: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10%
#
Symbol
Description
Notes
Min
Max
Units
1
T
C
PCLK period
30
ns
2
T
SU
Synchronous input setup to PCLK
1
7
ns
3
T
H
Synchronous input hold from PCLK
0
ns
4
T
COV
PCLK to output valid delay
2
3
11
ns
5
T
CZO
PCLK to output driving delay
4
11
ns
6
T
COZ
PCLK to high impedance delay
5
18
ns
7
T
RST
Reset period when PRST used as input
16
·
T
C
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