參數(shù)資料
型號(hào): V29C51001B-70J
廠商: MOSEL-VITELIC
元件分類: PROM
英文描述: 128K X 8 FLASH 5V PROM, 70 ns, PQCC32
封裝: PLASTIC, LCC-32
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 73K
代理商: V29C51001B-70J
MOSEL VITELIC
1
V29C51001T/V29C51001B
1 MEGABIT (131,072 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
PRELIMINARY
V29C51001T/V29C51001B Rev. 0.7 April 2000
Features
s 128Kx8-bit Organization
s Address Access Time: 45, 70, 90 ns
s Single 5V
± 10% Power Supply
s Sector Erase Mode Operation
s 8KB Boot Block (lockable)
s 512 bytes per Sector, 256 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Program Cycle Time: 20
s (Max)
s Minimum 10,000 Erase-Program Cycles
s Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100
A (Max)
s Hardware Data Protection
s Low VCC Program Inhibit Below 2.5V
s Self-timed program/erase operations with end-
of-cycle detection
– DATA Polling
– Toggle Bit
s CMOS and TTL Interface
s Available in two versions
– V29C51001T (Top Boot Block)
– V29C51001B (Bottom Boot Block)
s Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC
Description
The V29C51001T/V29C51001B is a high speed
131,072 x 8 bit CMOS flash memory. Programming
or erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, program enable WE, and output enable OE
controls to eliminate bus contention.
The V29C51001T/V29C51001B offers a combi-
nation of features: Boot Block with Sector Erase
Mode. The end of program/erase cycle is detected
by DATA Polling of I/O7 or by the Toggle Bit I/O6.
The V29C51001T/V29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector loaded either at the
top (V29C51001T) or the bottom (V29C51001B)
sector. All inputs and outputs are CMOS and TTL
compatible.
The V29C51001T/V29C51001B is ideal for
applications that require updatable code and data
storage.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
T
J
457090
Std.
0
°C to 70°C
Blank
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