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參數(shù)資料
| 型號： | V16DJ432BLT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 4M X 32 High Performance FPM Memory Module(4M X 32高性能FPM存儲器模塊) |
| 中文描述： | 4米× 32高性能程序手冊內(nèi)存模組（4米× 32高性能程序手冊存儲器模塊） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 53K |
| 代理商： | V16DJ432BLT |
8
V16DJX432BLT/V16DJ432BLT Rev. 0.1 February 1999
MOSEL V ITELIC
V16DJX432BLT/V16DJ432BLT
AC Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
Symbol
Parameter
V16DJX232BLT
Unit
Notes
Min.
Max.
1
t
RAS
RAS Pulse Width
50
75K
ns
2
t
RC
Read or Write Cycle Time
90
ns
3
t
RP
RAS Precharge Time
30
ns
4
t
CSH
CAS Hold Time
50
ns
5
t
CAS
CAS Pulse Width
9
ns
6
t
RCD
RAS to CAS Delay
19
36
ns
7
t
RCS
Read Command Setup Time
0
ns
4
8
t
ASR
Row Address Setup Time
0
ns
9
t
RAH
Row Address Hold Time
9
ns
10
t
ASC
Column Address Setup Time
0
ns
11
t
CAH
Column Address Hold Time
7
ns
12
t
RSH (R)
RAS Hold Time (Read Cycle)
15
ns
13
t
CRP
CAS to RAS Precharge Time
5
ns
14
t
RCH
Read Command Hold Time Referenced to CAS
0
ns
5
15
t
RRH
Read Command Hold Time Referenced to RAS
0
ns
5
16
t
CAC
Access Time from CAS (EDO)
14
ns
6, 7, 14
17
t
RAC
Access Time from RAS
50
ns
6, 8, 9
18
t
CAA
Access Time from Column Address
24
ns
6, 7, 10
19
t
LZ
CAS to Low-Z Output
0
ns
16
20
t
HZ
CAS to High-Z Output
0
8
ns
16
21
t
AR
Column Address Hold Time from RAS
40
ns
22
t
RAD
RAS to Column Address Delay Time
14
26
ns
11
23
t
RSH (W)
RAS or CAS Hold Time in Write Cycle
14
ns
24
t
CWL
Write Command to CAS Lead Time
14
ns
25
t
WCS
Write Command Setup Time
0
ns
12, 13
26
t
WCH
Write Command Hold Time
7
ns
27
t
WP
Write Pulse Width
7
ns
28
t
WCR
Write Command Hold Time from RAS
40
ns
29
t
RWL
Write Command to RAS Lead Time
14
ns
30
t
DS
Data in Setup Time
0
ns
14
31
t
DH
Data in Hold Time
7
ns
14
32
t
RWC
(RMW)
Read-Modify-Write Cycle Time
130
ns
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