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參數(shù)資料
| 型號： | V16DJ432BLT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 4M X 32 High Performance FPM Memory Module(4M X 32高性能FPM存儲器模塊) |
| 中文描述： | 4米× 32高性能程序手冊內(nèi)存模組（4米× 32高性能程序手冊存儲器模塊） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 53K |
| 代理商： | V16DJ432BLT |
10
V16DJX432BLT/V16DJ432BLT Rev. 0.1 February 1999
MOSEL V ITELIC
V16DJX432BLT/V16DJ432BLT
Notes:
1. I
CC
is dependent on output loading when the device output is selected. Specified I
CC
(max.) is measured with the
output open.
2.
I
CC
is dependent upon the number of address transitions. Specified I
CC
(max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified V
IL
(min.) is steady state operating. During transitions, V
IL
(min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with V
IL
(min.)
3
V
SS
and V
IH
(max.)
￡
V
CC
.
4. t
RCD
(max.) is specified for reference only. Operation within t
RCD
(max.) limits insures that t
RAC
(max.) and t
CAA
(max.) can be met. If t
RCD
is greater than the specified t
RCD
(max.), the access time is controlled by t
CAA
and t
CAC
.
5.
Either t
RRH
or t
RCH
must be satisified for a Read Cycle to occur.
6.
Measured with a load equivalent to one TTL inputs and 100 pF.
7.
Access time is determined by the longest of t
CAA
, t
CAC
and t
CAP
.
8.
Assumes that t
RAD
￡
t
RAD
(max.). If t
RAD
is greater than t
RAD
(max.), t
RAC
will increase by the amount that t
RAD
ex-
ceeds t
RAD
(max.).
9.
Assumes that t
RCD
￡
t
RCD
(max.). If t
RCD
is greater than t
RCD
(max.), t
RCD
will increase by the amount that t
RCD
ex-
ceeds t
RCD
(max.).
10.
Assumes that t
RAD
3
t
RAD
(max.).
11.
Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD
(max.) limit, the access time is controlled by t
CAA
and t
CAC
.
12.
t
WCS
, t
RWD
, t
AWD
and t
CWD
are not restrictive operating parameters.
13.
t
WCS
(min.) must be satisfied in an Early Write Cycle.
14.
t
DS
and t
DH
are referenced to the latter occurrence of CAS or WE.
15.
t
T
is measured between V
IH
(min.) and V
IL
(max.). AC-measurements assume t
T
= 3 ns.
16.
Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17.
An initial 200
m
s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
AC Characteristics (cont.)
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