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參數(shù)資料
| 型號： | V040K033T060 |
| 廠商： | Vicor Corporation |
| 元件分類： | DC/DC變換器 |
| 英文描述： | VI Chip - PRM-AL Pre-regulator Module |
| 中文描述： | 六芯片-大羅馬尼亞黨鋁預穩(wěn)壓模塊 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 544K |
| 代理商： | V040K033T060 |
vicorpower.com
800-735-6200
VI Chip Pre-Regulator Module
P048K048T24AL
Rev. 1.4
Page 9 of 15
PRELIMINARY
L
O
A
D
-In
PC
VC
TM
+In
-Out
+Out
VTM
+Out
-Out
K
Ro
+Out
–Out
+In
–In
VC
PC
TM
IL
NC
VH
SC
PR
SG
OS
NC
CD
PRM-AL
Factorized
Bus (V
f
)
Vout = V
L
± 2%
I
L
(I
L
Ro)
K
V
f
= V
L
+
K
Vin
R
OS
R
CD
0.4
μ
H
Output Voltage Setting with Adaptive Loop
The equations for calculating R
OS
and R
CD
to set a VTM output
voltage are:
93100
R
OS
=
(V
L
0.8395 ) – 1
K
(1)
R
CD
=
91238 + 1
R
OS
(2)
V
L
= Desired load voltage
V
OUT
= VTM output voltage
K = VTM transformation ratio
(available from appropriate VTM data sheet)
V
f
= PRM output voltage, the Factorized Bus (see Figure 14)
R
O
= VTM output resistance
(available from appropriate VTM data sheet)
I
L
= Load Current
(actual current delivered to the load)
Output Voltage Trimming (optional)
After setting the output voltage from the procedure above the output
may be margined down (26Vf min) by a resistor from SC-SG using this
formula:
R
d
Ω
=10000 V
fd
V
fs
- V
fd
Where V
fd
is the desired factorized bus and V
fs
is the set factorized bus.
A low voltage source can be applied to the SC port to margin the load
voltage in proportion to the SC reference voltage.
An external capacitor can be added to the SC port as shown in Figure 14 to
control the output voltage slew rate for soft start.
Figure 14
— Adaptive Loop compensation with soft start using the SC port.
Nominal Vout
Range (Vdc)
VTM
K Factor
0.8
1.1
1.6
2.2
3.3
4.3
6.5
8.7
13.0
17.4
26.0
1.6
2.2
3.3
4.4
6.6
8.8
13.4
17.9
26.9
36.0
54.0
1/32
1/24
1/16
1/12
1/8
1/6
1/4
1/3
1/2
2/3
1
Table 2
— 048 input series VTM K factor selection guide
Application Information
VI Chip Pre-Regulator Module
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