
UTC571
LINEAR INTEGRATED CIRCUIT
YOUWANG ELECTRONICS CO.LTD
8
CIRCUIT DETAILS—RECTIFIER
R1
V
IN
I=V
IN
/R1
V+
RS
10K
C
R
I
G
Figure 5. Rectifier Concept
Figure 5 shows the concept behind the full-wave averaging rectifier. The input current to the summing node of
the op amp, V
IN
R 1 , is supplied by the output of the op amp. If we can mirror the op amp output current into a
unipolar current, we will have an ideal rectifier. The output current is averaged by R5 , CR, which set the averaging
time constant, and then mirrored with a gain of 2 to become I
G
, the gain control current.
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
D1
I
1
I
2
C
R
R1
10K
R
S
10K
V
IN
Figure 6. Simplified Rectifier Schematic
Figure 6 shows the rectifier circuit in more detail. The op amp is a one-stage op amp, biased so that only one
output device is on at a time. The non-inverting input, (the base of Q 1 ), which is shown grounded, is actually tied
to the internal 1.8V V
REF
. The inverting input is tied to the op amp output, (the emitters of Q 5 and Q 6 ), and the
input summing resistor R 1 . The single diode between the bases of Q 5 and Q 6 assures that only one device is on
at a time. To detect the output current of the op amp, we simply use the collector currents of the output devices Q
5 and Q 6 . Q 6 will conduct when the input swings positive and Q 5 conducts when the input swings negative. The
collector currents will be in error by the a of Q 5 or Q 6 on negative or positive signal swings, respectively. ICs such
as this have typical NPN bs of 200 and PNP bs of 40. The a’s of 0.995 and 0.975 will produce errors of 0.5% on
negative swings and 2.5% on positive swings. The 1.5%
average of these
errors yields a mere 0.13dB gain error.