UTC 4053 CMOS IC
PARAMETER
SYMBOL
TEST CONDITIONS
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to V
SS
)
Ron= per spec, Ioff = per spec
V
DD
=5.0V
V
DD
=10V
V
DD
=15V
Ron= per spec, Ioff = per spec
V
DD
=5.0V
V
DD
=10V
V
DD
=15V
Input Leakage Current
Iin
Vin= 0 or V
DD
, V
DD
=15V
Input Capacitance
Cin
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to V
EE
)
Recommended Peak–to–Peak Voltage
Into or Out of the Switch
Recommended Static or Dynamic
Voltage Across the Switch** (Figure 3)
Output Offset Voltage
V
OO
Vin = 0V, No Load
Vswitch
≦
500mV*
Vin = V
IL
or V
IH
(Control), and
Vin = 0 to V
DD
(Switch)
V
DD
=5.0V
V
DD
=10V
V
DD
=15V
V
DD
=5.0V
V
DD
=10V
V
DD
=15V
Vin = V
IL
or V
IH
(Control)
Channel to Channel or Any
One Channel, V
DD
=15V
Capacitance, Switch I/O
C
I/O
Inhibit = V
DD
Capacitance, Common O/I
C
O/I
Inhibit = V
DD
Capacitance, Feedthrough
(Channel Off)
Pins Adjacent
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential
performance.
* For voltage drops across the switch (
Vswitch) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may
be drawn, i.e. the current out of the switch may contain both V
DD
and switch input components. The reliability of the
device will be unaffected unless the Maximum Ratings are exceeded. (See second page of this data sheet.)
UTC
UNISONIC TECHNOLOGIES CO., LTD.
3
www.unisonic.com.tw
QW-R502-036,A
MIN
TYP#
MAX
UNIT
Low – Level Input Voltage
V
IL
2.25
4.50
6.75
2.75
5.50
8.25
1.5
3.0
4.0
V
High – Level Input Voltage
V
IH
3.5
7.0
11
V
±0.00001
5.0
±0.1
7.5
μA
pF
V
I/O
Channel On or Off
0
V
DD
V
PP
Vswitch
Channel On
0
600
mV
10
250
120
80
25
10
10
μV
ON Resistance
Ron
1050
500
280
70
50
45
Δ
ON Resistance Between Any Two
Channels in the Same Package
Ron
Off–Channel Leakage Current
(Figure 8)
Ioff
±0.05
±100
nA
10
17
0.15
0.47
pF
pF
C
I/O
Pins Not Adjacent
pF