參數(shù)資料
型號: UT7C138C55GCX
英文描述: SRAM|4KX8|CMOS| RAD HARD|PGA|68PIN|CERAMIC
中文描述: 靜態(tài)存儲器| 4KX8 |的CMOS | RAD數(shù)據通信硬|美巡賽| 68PIN |陶瓷
文件頁數(shù): 6/21頁
文件大小: 272K
代理商: UT7C138C55GCX
6
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation
)*
(V
DD
= 5.0V
±
10%; -55
°
C < T
C
< +125
°
C)
SYMBOL
PARAMETER
Notes:
* Post-radiation performance guaranteed at 25
°
C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. V
IH
= 5.5V, V
IL
= 0V.
5. I
DD
(OP) derates at 6.4mA/MHz.
6. I
DD
(OP) derates at 3.4mA/MHz.
CONDITION
MIN
MAX
UNIT
V
IH
High-level input voltage
(CMOS)
0.7V
DD
V
V
IL
Low-level input voltage
(CMOS)
0.3V
DD
V
V
OL
Low-level output voltage
I
OL
= 8mA, V
DD
= 4.5V (TTL)
0.4
V
V
OL
Low-level output voltage
I
OL
= 200
μ
A, V
DD
= 4.5V (CMOS)
0.05
V
V
OH
High-level output voltage
I
OH
= -4mA, V
DD
= 4.5V (TTL)
2.4
V
V
OH
High-level output voltage
I
OH
= -200
μ
A, V
DD
= 4.5V (CMOS)
4.45
V
C
IN
1
Input capacitance
= 1MHz @ 0V
25
pF
C
IO
1
Bidirectional I/O capacitance
= 1MHz @ 0V
25
pF
I
IN
Input leakage current
V
IN
= V
DD
and V
SS
-10
10
μ
A
I
OZ
Three-state output leakage current
V
O
= V
DD
and V
SS
V
DD
= 5.5V
G = 5.5V
-10
10
μ
A
I
OS
2,3
Short-circuit output current
V
DD
= 5.5V, V
O
= V
DD
V
DD
= 5.5V, V
O
= 0V
-90
90
mA
mA
I
DD
(OP)
4,5
Supply current operating (both ports)
@ 22.2MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
300
mA
I
DD
(OP)
4,6
Supply current operating (single port)
@ 22.2 MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
150
mA
I
DD
(OP)
4,5
Supply current operating (both ports)
@ 18.2MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
275
mA
I
DD
(OP)
4,6
Supply current operating (single port)
@ 18.2 MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
138
mA
I
DD
(SB)
4
Supply current standby
CMOS inputs (I
OUT
= 0)
CE = V
DD
- 0.5,
V
DD
= 5.5V
1
mA
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