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參數(shù)資料
| 型號： | UT62256C(E) |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 94K |
| 代理商： | UT62256C(E) |
UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
tAA
Data Valid
Address
Dout
tOH
Previous data valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tOE
tOHZ
tCLZ
tOH
tOLZ
High-Z
Data Valid
High-Z
tCHZ
Address
Dout
CE
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selected OE =low, CE =low.
3.Address must be valid prior to or coincident with CE =low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ is less than tOHZ is less than tOLZ.
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