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參數(shù)資料
| 型號： | UT54ACTS20-UVAH |
| 元件分類： | 門電路 |
| 英文描述： | ACT SERIES, DUAL 4-INPUT NAND GATE, CDFP14 |
| 封裝： | FP-14 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 25K |
| 代理商： | UT54ACTS20-UVAH |
RadHard MSI Logic
32
UT54ACS20/UT54ACTS20
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
AC ELECTRICAL CHARACTERISTICS
2
(V
DD
= 5.0V 10%; V
SS
= 0V
1
, -55 C < T
C
< +125 C)
SYMBOL
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
PHL
Input to Yn
1
15
ns
t
PLH
Input to Yn
1
11
ns
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