- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381210 > UT22VP10C-20PCA MD516 DDP 32Gb x8 1.8V TSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | UT22VP10C-20PCA |
| 英文描述： | MD516 DDP 32Gb x8 1.8V TSOP |
| 中文描述： | 保險(xiǎn)絲，可編程的PLD |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | UT22VP10C-20PCA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
12
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be
reset to LOW after the device has been powered up. The output
state will depend on the programmed pattern. This feature is
valuable in simplifying state machine initialization. See figure
6 for a timing diagram. Due to the synchronous operation of the
power-up reset and the wide range of ways V
DD
can rise to its
steady state, the following five conditions are required to ensure
a valid power-up reset.
1. The voltage supplied to the V
DD
pin(s) must be equal to 0V
prior to the intended power-up sequence.
2. The voltage on V
DD
must rise from 0V to 1V at a rate of
0.1V/s or faster.
3. The V
DD
rise must be continuously increasing with respect
to time, through 3V, and monotonic thereafter.
4. Following reset, the clock input must not be driven from
LOW to HIGH until all applicable input and feedback setup
times are met.
5. The power-up voltage must meet the minimum V
DD
require-
ments described by the following device dependent and tem-
perature dependent equations:
RADIATION HARDNESS
The UT22VP10 RAD
PAL
incorporates special design and layout features which allow operation in high-level radiation environments.
UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both
the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup
immunity, UTMC builds radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process.
RADIATION HARDNESS
DESIGN SPECIFICATIONS
1
Note:
1. The RAD
PAL
will not latchup during radiation exposure under recommended operating conditions.
SMD Device types 01, 02, 03, 04, 08
V
DD
=4.61V -0.0090*(
o
C)
SMD Device types 05, 06, 07
V
DD
=4.41 -0.0090* (
o
C)
Note: The minimum V
DD
requirement above is not applicable
if the UT22VP10 application is purely combinatorial (i.e. no
registered outputs).
CMOS and TTL
CMOS
V
DD
REGISTERED
ACTIVE-LOW
OUTPUT
CLOCK
V
DD
t
WL
V
DD
min
t
PR
t
S
Figure 6. Power-Up Reset Waveform
PARAMETER
CONDITION
MINIMUM
UNIT
Total Dose
+25
°
C per MIL-STD-883 Method 1019
1.0E6
rads(Si)
LET Threshold
-55
°
C to +125
°
C
50
MeV-cm
2
/mg
Neutron Fluence
1MeV equivalent
1.0E14
n/cm
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT22VP10C-20PCC | MD516 QDP 64Gb x8 1.8V TSOP |
| UT22VP10C-20PCX | MD516 SDP 16Gb x8 1.8V TSOP |
| UT22VP10C-20UCA | MD516 SDP 16Gb x8 1.8V TSOP |
| UT22VP10C-20UCC | MD78 SDP 08Gb x8 1.8V TSOP |
| UT22VP10C-20UCX | Fuse-Programmable PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT22VP10C-20PCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| UT22VP10C-20PCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| UT22VP10C-20UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| UT22VP10C-20UCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| UT22VP10C-20UCX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。