參數(shù)資料
型號(hào)： US5A10AS17K
廠商： NEC Corp.
元件分類： 4位微控制器
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 4位單片機(jī)的小型通用紅外遙控器
文件頁(yè)數(shù)： 51/289頁(yè)
文件大?。?/td> 832K
代理商： US5A10AS17K
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CHAPTER 6 STACK
36
6.3 ADDRESS STACK REGISTER
As shown in Figure 6-1, the address stack register consists of five consecutive 10-bit registers.
A value equal to the program counter (PC)+1 (return address) is stored during execution of subroutine calls (CALL
addr, CALL @AR), the first cycle of a table reference (MOVT DBF, @AR), and upon receipt of an interrupt in the address
stack register. The contents of the address register (AR) is also stored when a stack push (PUSH AR) is executed.
The address register holding data is pointed to by the address in the stack pointer at execution time less one (address
in stack pointer (SP) – 1).
When a subroutine return (RET, RETSK), an interrupt return (RETI), or the second cycle of a table reference (MOVT
DBF, @AR) is executed, the contents of the address pointed to by the stack pointer is restored to the program counter
and the stack pointer is incremented. When a stack pop (POP AR) is executed, the value in the address stack register
pointed to by the stack pointer is transferred to the address to the address register and the stack pointer is
incremented.
If more than five subroutine calls or interrupts are executed,
an internal reset signal is generated, and the
address stack register initializes hardware for start at address 0000H
(to prevent a software crash).
6.4 INTERRUPT STACK REGISTER
As shown in Figure 6-1, the interrupt stack register consists of one 5-bit register.
When an interrupt is received five bits in the system register (SYSREG) (mentioned later) that is, each flag (BCD,
CMP, CY, Z, IXE) of the program status word (PSWORD), are saved. When the interrupt return (RETI) is executed,
the program status word is restored from the interrupt stack register.
In the interrupt stack register, every time an interrupt is received, necessary data is saved.
When more than three interrupts are received, the data from the first interrupt is lost.
Remark
All the 5 bits of PSWORD are automatically cleared to zero after being saved in the interrupt stack
register.
6.5 STACK POINTER (SP) AND INTERRUPT STACK REGISTER
As shown in Figure 6-1, the stack pointer (SP) is a 3-bit binary counter used to point to addresses in the five address
stack registers. The stack pointer is located at address 01H in the register file. At reset, the stack pointer is set
to 5.
As shown in Table 6-1, the stack pointer is decremented when subroutine calls (CALL addr, CALL @AR), the first
cycle of a table reference (MOVT DBF, @AR), stack push (PUSH AR), and an interrupt are accepted. The stack pointer
is incremented at the following times: subroutine returns (RET, RETSK), the second instruction cycle of a table
reference (MOVT DBF, @AR), stack pop (POP AR), and an interrupt return (RETI). The interrupt stack counter as
well as the stack pointer is decremented when an interrupt is accepted. The interrupt stack counter is incremented
by an interrupt return (RETI) only.
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