參數資料
型號: US1881LSE-AAA-000-RE
廠商: Melexis Technologies NV
文件頁數: 5/7頁
文件大小: 1194K
描述: IC LATCH CMOS MP TSOT23-3
產品目錄繪圖: TSOT-3L Series Top
標準包裝: 1
傳感范圍: 9.5mT 跳閘,-9.5mT 釋放
類型: 雙極卡鎖
電源電壓: 3.5 V ~ 24 V
電流 - 電源: 5mA
電流 - 輸出(最大): 50mA
輸出類型: 數字式,開漏極
工作溫度: -40°C ~ 150°C
封裝/外殼: TO-236-3,SC-59,SOT-23-3
供應商設備封裝: TSOT-23-3
包裝: 標準包裝
產品目錄頁面: 2792 (CN2011-ZH PDF)
其它名稱: US1881LSE-AAA-000-REDKR
US1881LSEDKR
US1881LSEDKR-ND
US188LESE-AAA-000-REDKR-ND
 
1
Rev 016
 
 
 
9 Detailed General Desc i
 
Based on mixed signal CMOS techn
sensitivity. This multi-purpose latch s
 
The chopper-stabilized amplifier uses
with Hall sensors and amplifiers. The
contributes to smaller chip size and l
also an important factor to minimize t
This combination results in more stab
 
The wide operating voltage fro
.  V
temperature range according to L, 
industrial and consumer applications.
 
The output signal is open-drain type.
a pull-up resistor tied between a pull-
 
10 Unique Features 
 
The US1881 exhibits latch magnetic
poles to operate properly.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
SE package - Latch characteri
 
The device behaves as a latch with s
means magnetic fields with equival  n
 
Removing the magnetic field (B?) k
device as a magnetic memory.
 
A magnetic hysteresis B
HYST
keeps B
output oscillation near the switching
Hall Latch  Hi
f 12
ption 
logy, Melexis US1881 is a Hall-effect device with hi
its most of the application requirements.
switched capacitor technique to suppress the offset
MOS technology makes this advanced technique
wer current consumption than bipolar technology. T
e effect of physical stress.
e magnetic characteristics and enables faster and
 to 24V, low current consumption and large choice
 and E specification make this device suitable for
uch output allows simple connectivity with TTL or
p voltage and the device output.
witching characteristics. Therefore, it requires both
tic
UA package - Latch c
mmetric operating and release switching points (B
O
 strength and opposite direction drive the output hig
 the output in its previous state. This latching p
 
and B
RP
separated by a minimal value. This hyste
int.
S
1
h Sensitivity
Mar/12
 magnetic
generally observed
ssible and
 small chip size is
ore precise design.
perating
automotive,
MOS logic by using
outh and north
teristic
=|B
RP
|). This
 and low.
operty defines the
esis prevents
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