參數(shù)資料
型號(hào)： UPSD3432E
廠商： 意法半導(dǎo)體
英文描述： Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
中文描述： Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器
文件頁(yè)數(shù)： 68/264頁(yè)
文件大?。?/td> 4320K
代理商： UPSD3432E
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uPSD34xx - SUPERVISORY FUNCTIONS
68/264
Low V
CC
Voltage Detect, LVD
An internal reset is generated by the LVD circuit
when V
CC
drops below the reset threshold,
V
LV_THRESH
. After V
CC
returns to the reset thresh-
old, the MCU_RESET signal will remain asserted
for t
RST_ACTV
before it is released. The LVD circuit
is always enabled (cannot be disabled by SFR),
even in Idle Mode and Power-down Mode. The
LVD input has a voltage hysteresis of V
RST_HYS
and will reject voltage spikes less than a duration
of t
RST_FIL
.
Important:
The LVD voltage threshold is
V
LV_THRESH
, suitable for monitoring both the 3.3V
V
CC
supply on the MCU Module and the 3.3V V
DD
supply on the PSD Module for 3.3V uPSD34xxV
devices, since these supplies are one in the same
on the circuit board.
However, for 5V uPSD34xx devices, V
LV_THRESH
is not suitable for monitoring the 5V V
DD
voltage
supply (V
LV_THRESH
is too low), but good for mon-
itoring the 3.3V V
CC
supply. In the case of 5V
uPSD34xx devices, an external means is required
to monitor the separate 5V V
DD
supply, if desired.
Power-up Reset
At power up, the internal reset generated by the
LVD circuit is latched as a logic '1' in the POR bit
of the SFR named PCON (
Table 26., page 52
).
Software can read this bit to determine whether
the last MCU reset was the result of a power up
(cold reset) or a reset from some other condition
(warm reset). This bit must be cleared with soft-
ware.
JTAG Debug Reset
The JTAG Debug Unit can generate a reset for de-
bugging purposes. This reset source is also avail-
able when the MCU is in Idle Mode and Power-
Down Mode (the user can use the JTAG debugger
to exit these modes).
Watchdog Timer, WDT
When enabled, the WDT will generate a reset
whenever it overflows. Firmware that is behaving
correctly will periodically clear the WDT before it
overflows. Run-away firmware will not be able to
clear the WDT, and a reset will be generated.
By default, the WDT is disabled after each reset.
Note:
The WDT is not active during Idle mode or
Power-down Mode.
There are two SFRs that control the WDT, they are
WDKEY (
Table 39., page 70
) and WDRST (
Table
40., page 70
).
If WDKEY contains 55h, the WDT is disabled. Any
value other than 55h in WDKEY will enable the
WDT. By default, after any reset condition, WD-
KEY is automatically loaded with 55h, disabling
the WDT. It is the responsibility of initialization
firmware to write some value other than 55h to
WDKEY after each reset if the WDT is to be used.
The WDT consists of a 24-bit up-counter (Figure
24
), whose initial count is 000000h by default after
every reset. The most significant byte of this
counter is controlled by the SFR, WDRST. After
being enabled by WDKEY, the 24-bit count is in-
creased by 1 for each MCU machine cycle. When
the count overflows beyond FFFFFh (2
24
MCU
machine cycles), a reset is issued and the WDT is
automatically disabled (WDKEY = 55h again).
To prevent the WDT from timing out and generat-
ing a reset, firmware must repeatedly write some
value to WDRST before the count reaches
FFFFFh. Whenever WDRST is written, the upper
8 bits of the 24-bit counter are loaded with the writ-
ten value, and the lower 16 bits of the counter are
cleared to 0000h.
The WDT time-out period can be adjusted by writ-
ing a value other that 00h to WDRST. For exam-
ple, if WDRST is written with 04h, then the WDT
will start counting 040000h, 040001h, 040002h,
and so on for each MCU machine cycle. In this ex-
ample, the WDT time-out period is shorter than if
WDRST was written with 00h, because the WDT
is an up-counter. A value for WDRST should never
be written that results in a WDT time-out period
shorter than the time required to complete the
longest code task in the application, else unwant-
ed WDT overflows will occur.
Figure 24. Watchdog Counter
23
15
7
0
8-bits
8-bits
8-bits
SFR, WDRST
AI09604
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