uPSD34xx - I/O PORTS of MCU MODULE
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I/O PORTS OF MCU MODULE
The MCU Module has three 8-bit I/O ports: Port 1,
Port 3, and Port 4. The PSD Module has four other
I/O ports: Port A, B, C, and D. This section de-
scribes only the I/O ports on the MCU Module.
I/O ports will function as bi-directional General
Purpose I/O (GPIO), but the port pins can have al-
ternate functions assigned at run-time by writing to
specific SFRs. The default operating mode (during
and after reset) for all three ports is GPIO input
mode. Port pins that have no external connection
will not float because each pin has an internal
weak pull-up (~150K ohms) to V
CC
.
I/O ports 3 and 4 are 5V tolerant, meaning they
can be driven/pulled externally up to 5.5V without
damage. The pins on Port 4 have a higher current
capability than the pins on Ports 1 and 3.
Three additional MCU ports (only on 80-pin
uPSD34xx devices) are dedicated to bring out the
8032 MCU address, data, and control signals to
external pins. One port, named MCUAD[7:0], has
eight multiplexed address/data bidirectional sig-
nals. The third port has MCU bus control outputs:
read, write, program fetch, and address latch.
These ports are typically used to connect external
parallel peripherals and memory devices, but they
may NOT be used as GPIO. Notice that the eight
upper address signals do not come out to pins on
the port. If high-order address signals are required
on external pins (MCU addresses A[15:8]), then
these address signals can be brought out as need-
ed to PLD output pins or to the Address Out mode
pins on PSD Module ports. See PSD Module sec-
tion, “
Latched Address Output Mode, page 208
for
details.
Figure 16., page 56
represents the flexibility of pin
function routing controlled by the SFRs. Each of
the 24 pins on three ports, P1, P3, and P4, may be
individually routed on a pin-by-pin basis to a de-
sired function.
MCU Port Operating Modes
MCU port pins can operate as GPIO or as alter-
nate functions (see
Figure 17., page 57
through
Figure 19., page 58
).
Depending on the selected pin function, a particu-
lar pin operating mode will automatically be used:
GPIO - Quasi-bidirectional mode
UART0, UART1 - Quasi-bidirectional mode
SPI - Quasi-bidirectional mode
I2C - Open drain mode
ADC - Analog input mode
PCA output - Push-Pull mode
PCA input - Input only (Quasi-bidirectional)
Timer 0,1,2 - Input only (Quasi-bidirectional)
GPIO Function.
Ports in GPIO mode operate as
quasi-bidirectional pins, consistent with standard
8051 architecture. GPIO pins are individually con-
trolled by three SFRs:
SFR, P1 (
Table 27., page 58
)
SFR, P3 (
Table 28., page 59
)
SFR, P4 (
Table 29., page 59
)
These SFRs can be accessed using the Bit Ad-
dressing mode, an efficient way to control individ-
ual port pins.
GPIO Output.
Simply stated, when a logic '0' is
written to a bit in any of these port SFRs while in
GPIO mode, the corresponding port pin will enable
a low-side driver, which pulls the pin to ground,
and at the same time releases the high-side driver
and pull-ups, resulting in a logic '0' output. When a
logic '1' is written to the SFR, the low-side driver is
released, the high-side driver is enabled for just
one MCU_CLK period to rapidly make the 0-to1
transition on the pin, while weak active pull-ups
(total ~150K
) to V
CC
are enabled. This structure
is consistent with standard 8051 architecture. The
high side driver is momentarily enabled only for 0-
to-1 transitions, which is implemented with the de-
lay function at the latch output as pictured in
Fig-
ure 17., page 57
,
Figure 18., page 57
, and
Figure
19., page 58
. After the high-side driver is disabled,
the two weak pull-ups remain enabled resulting in
a logic '1' output at the pin, sourcing I
OH
uA to an
external device. Optionally, an external pull-up re-
sistor can be added if additional source current is
needed while outputting a logic '1.'
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