參數(shù)資料
型號(hào)： UPSD3424E-40U6T
廠商： 意法半導(dǎo)體
英文描述： Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
中文描述： Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器
文件頁(yè)數(shù)： 47/264頁(yè)
文件大小： 4320K
代理商： UPSD3424E-40U6T
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uPSD34xx - MCU CLOCK GENERATION
MCU CLOCK GENERATION
Internal system clocks generated by the clock gen-
eration unit are derived from the signal, XTAL1,
shown in Figure
14
. XTAL1 has a frequency f
OSC
,
which comes directly from the external crystal or
oscillator device. The SFR named CCON0 (
Table
22., page 49
) controls the clock generation unit.
There are two clock signals produced by the clock
generation unit:
MCU_CLK
PERIPH_CLK
MCU_CLK
This clock drives the 8032 MCU core and the
Watchdog Timer (WDT). The frequency of
MCU_CLK is equal to f
OSC
by default, but it can be
divided by as much as 2048, shown in Figure
14
.
The bits CPUPS[2:0] select one of eight different
divisors, ranging from 2 to 2048. The new frequen-
cy is available immediately after the CPUPS[2:0]
bits are written. The final frequency of MCU_CLK
is f
MCU
.
MCU_CLK is blocked by either bit, PD or IDL, in
the SFR named PCON during MCU Power-down
Mode or Idle Mode respectively.
MCU_CLK clock can be further divided as re-
quired for use in the WDT. See details of the WDT
in
SUPERVISORY FUNCTIONS, page 67
.
PERIPH_CLK
This clock drives all the uPSD34xx peripherals ex-
cept the WDT. The Frequency of PERIPH_CLK is
always f
OSC
. Each of the peripherals can indepen-
dently divide PERIPH_CLK to scale it appropriate-
ly for use.
PERIPH_CLK runs at all times except when
blocked by the PD bit in the SFR named PCON
during MCU Power-down Mode.
JTAG Interface Clock.
The JTAG interface for
ISP and for Debugging uses the externally sup-
plied JTAG clock, coming in on pin TCK. This
means the JTAG ISP interface is always available,
and the JTAG Debug interface is available when
enabled, even during MCU Idle mode and Power-
down Mode.
However, since the MCU participates in the JTAG
debug process, and MCU_CLK is halted during
Idle and Power-down Modes, the majority of de-
bug functions are not available during these low
power modes. But the JTAG debug interface is ca-
pable of executing a reset command while in these
low power modes, which will exit back to normal
■
■
operating mode where all debug commands are
available again.
The CCON0 SFR contains a bit, DBGCE, which
enables the breakpoint comparators inside the
JTAG Debug Unit when set. DBGCE is set by de-
fault after reset, and firmware may clear this bit at
run-time. Disabling these comparators will reduce
current consumption on the MCU Module, and it is
recommended to do so if the Debug Unit will not
be used (such as in the production version of an
end-product).
USB_CLK.
The uPSD34xx has a dedicated ana-
log phase locked loop (PLL) that can be config-
ured to generate the 48MHz USB_CLK clock on a
wide range of f
OSC
frequencies. The USB_CLK
must be at 48MHz for the USB to function proper-
ly.
The PLL is enabled after power up. The power on
lock time for the PLL clock is about 200μs, and the
firmware should wait that much time before en-
abling the USB_CLK by setting the USBCE Bit in
the CCON0 Register to '1.' The PLL is disabled in
Power-down mode, it can also be disabled or en-
abled by writing to the PLLEN Bit in the CCON0
Register.
The PLL output clock frequency (f
USB_CLK
) can be
determined by using the following formula:
f
USBCLK
PLLD
+
(
[
where PLLM and PLLD are the multiplier and divi-
sor that are specified in the CCON1 Register. The
f
OSC
, the PLLM and PLLD range must meet the
following conditions to generate a stable
USB_CLK:
a.
–1
≤
PLLM
≤
30 (binary: [11111]
≤
PLLM[4:0]
≤
[11110]),
b.
–1
≤
PLLD
≤
14 (binary: [1111]
≤
PLLD[3:0]
≤
[1110]), and
c.
f
OSC
/(PLLD+2) must be equal to or greater
than 3MHz.
The USB requires a 48MHz clock to operate cor-
rectly. The PLLM[4:0] and PLLD[3:0] values must
be selected so as to generate a USB_CLK that is
as close to 48MHz as possible at different oscilla-
tor frequencies (f
OSC
).
Table 21., page 48
lists
some of the PLLM and PLLD values that can be
used on common f
OSC
frequencies.
f
OSC
PLLM
2
)
2
+
]
(
)
×
[
]
2
×
=
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參數(shù)描述
UPSD3433E-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433E-40U6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40T6 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40U6 功能描述:8位微控制器 -MCU uPSD34x Turbo Plus Fast Turbo 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EV-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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